Advance Information
Device Overview
The LDX is capable of switching 2,048
×
2,048
channels. The device is designed to switch 64 or N x
64 kbit/s data. It can provide frame integrity for data
applications and minimum throughput switching
delay for voice application on a per channel basis.
The serial input streams of LDX can operate at
2.048, 4.096 and 8.192 Mbit/s and are arranged in
125µs wide frames which contains 32, 64 and 128
channels, respectively. The LDX automatically
identifies the polarity of the input frame
synchronization signal and configures the serial
ports to be compatible to either ST-BUS and GCI
formats. The input and output streams accept
identical data rates only.
By using Mitel message mode capability, the
microprocessor can access input and output time-
slots on a per channel basis to control external
circuits or other ST-BUS devices. Two different
microprocessor bus interface can be selected
through an input mode pin (IM): Non-multiplexed or
Multiplexed. These interfaces provide compatibility
with Intel/National multiplexed and Motorola
Multiplexed/Non-multiplexed buses.
The frame offset calibration allows users to measure
the frame offset delay using an frame evaluation pin
(FE). The input stream offset delay can be
individually programmed using internal registers.
CMOS
MT90820
Locations in the connect memory are associated with
particular output streams. When a channel is due to
be transmitted on an output, the data for the channel
can either be switched from an input as in
connection mode or it can be from the connect
memory as in message mode. Data destined for a
particular channel on the serial output stream is read
from the data memory or connect memory during the
previous channel time-slot. This allows enough time
for memory access and parallel to serial conversion.
Connection and Message Modes
In Connection mode, the addresses of the inputs for
all output channels are stored in the connect
memory. Once the source addresses are
programmed by the CPU, the contents of the data
memory at the selected address are transferred to
the parallel-to-serial inverters. By having the output
channel specifying the source channel through the
connect memory, the user can route the same input
channel to serval output channels, allowing
broadcast facility within the switch.
In message mode, the CPU writes data to the
connect memory locations corresponding to the
output link and channel number. The lower half (8-
LSBs) of the connect memory content is transferred
directly to the parallel-to-serial converter one
channel before it is to be output. The data is
transmitted on to the output every frame until it is
changed by the CPU with a new data.
The five most significant bits in the connect memory
determine individual output channel to be in
message or connection mode, select output
throughput delay type, enable/disable output drivers
and enable/disable the loopback mode. In addition,
one of these bits allows the user to control the CSTo
output.
If an output channel is set to high-impedance, the
TDM serial stream output will be in high impedance
during that channel time. In addition to the per-
channel control, all channels on the TDM outputs
can be placed in high impedance by either pulling
the ODE input pin low or programming a particular
bit in the control register.
The connect memory data is received via the
microprocessor interface through the data I/O bus.
The addressing of the LDX internal registers, data
and connect memories is performed through address
input pins and the Memory Select bit in the control
register.
Functional Description
A functional Block Diagram of the LDX device is
shown in Figure 1. Depending upon the application,
the LDX device receives TDM serial data at different
rates.
Data and Connect Memory
For all data rates, the received serial data is
converted to parallel format by the serial to parallel
converters and stored sequentially in a Data
Memory. Depending upon the selected operation, the
data memory may have up to 2,048 bytes in use. The
sequential addressing of the data memory is
performed by an internal counter which is reset by
the input 8 kHz frame pulse (FRM) marking the
frame boundaries of the incoming serial data
streams.
Data to be output on the serial streams may come
from two sources: Data Memory or Connect Memory.
2-183
MITEL [ MITEL NETWORKS CORPORATION ]
