MT90820
A7
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMOS
Advance Information
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
A5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
.
1
1
A4
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
A3
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
A2
0
0
0
0
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
A1
0
0
1
1
0
0
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
A0
0
1
0
1
0
1
0
0
1
.
0
1
0
1
.
0
1
0
1
.
0
1
Location
Control Register, CAR.
Interface Mode Selection register, IMS
Frame Alignment register, FAR
Frame Input Offset register 0, FOS0
Frame Input Offset register 1, FOS1
Frame Input Offset register 2, FOS2
Frame Input Offset register 3, FOS3
Ch 0*
Ch 1*
.
Ch 30*
Ch 31*
Ch 32**
Ch 33**
.
Ch 62**
Ch 63**
Ch 64***
Ch 65***
.
Ch 126***
Ch 127***
Note 1: The bit A7 must be retained HIGH for accesses to Data and Connection Memory positions.
The bit A7 must be retained LOW for accesses to Registers.
Note*: Channel 0 to 31 are used in 2Meg mode.
Note**: Channel 0 to 63 are used in 4Meg mode.
Note***: Channel 0 to 127 are used in 8Meg mode.
Table 2 - Internal Register and Address Memory Mapping
2-186
MITEL [ MITEL NETWORKS CORPORATION ]
