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MT90820 参数 Datasheet PDF下载

MT90820图片预览
型号: MT90820
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS ?系列大型数字交换机( LDX ) [CMOS ST-BUS⑩ FAMILY Large Digital Switch (LDX)]
分类和应用:
文件页数/大小: 10 页 / 73 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information
Pin Description
Pin #
84
1, 11,
30, 54
64, 75
100
31,
41,
56,
66,
76, 99
5, 40,
67
68-75
81-96
97
Name
V
SS
Ground.
Description
CMOS
MT90820
2, 32,
63
3 - 10
12 -
27
28
V
DD
STo8 - 15
STi0 - 15
FRM
+5 Volt Power Supply.
Data Stream Output 8 to 15: Serial data Output stream.
These stream may
have data rates of 2.048, 4.096 or 8.192 Mb/s.
Data Stream Input 0 to 15: Serial data input stream.
These stream may have
data rates of 2.048, 4.096 or 8.192.
Frame Pulse (input):
This input accepts and automatically identifies frame
synchronization signals formatted according to ST-BUS and GCI interface
specifications, when HMVIP pin =0.
When HMVIP pin =1, FRM input accepts a negative frame pulse which conforms
to HMVIP formats.
Frame Measurement input,
when HMVIP pin = 0.
4.096MHz Clock input,
when HMVIP pin = 1.
Clock (input):
Serial clock for shifting data in/out on the serial stream.
When 1, enable test mode for production testing.
Test Data Input.
Test Data Output.
Test Clock input.
Test Reset Input:
When 0, resets the test circuit.
Internal Connection:
keep at 0 for normal operation.
Device Reset Input:
When 0, resets the device.
HMVIP mode input.
When 1, enables HMVIP interface.
When 0, the device operates in ST-BUS/GCI mode.
Address 0 - 7(Input):
When non-multiplexed CPU bus is selected, these lines
provide the A0 - A7 address lines to internal memories.
Data Strobe/Read (input):
When non-multiplexed CPU bus or Motorola
multiplexed bus are selected, this input is DS. This active high input works in
conjunction with CSB to enable read and write operation.
For Intel multiplexed bus, this input is RDB. This active low input sets the data bus
lines (AD0-AD7, D8-D15) as outputs.
Read/Write \ Write (Input):
In case of non-multiplexed and Motorola multiplexed
buses, this input is Read/Write. This input controls the direction of the data bus
lines (AD0 - AD7, D8-D15) during a microprocessor access.
Chip Select (Input):
Active low input enabling a microprocessor access of the
device.
29
31
33
34
35
36
37
38
39
40
41 -
48
49
98
100
6
7
8
9
10
11
12
13
14-21
22
FE/HCLK
CLK
TMS
TDI
TDO
TCK
TRSTB
IC
RESETB
HMVIP
A0 - A7
DS/RD
50
23
R/W\WR
51
24
CS
2-181