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MT9080AP 参数 Datasheet PDF下载

MT9080AP图片预览
型号: MT9080AP
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS SMX - 交换矩阵模块 [CMOS SMX - Switch Matrix Module]
分类和应用:
文件页数/大小: 24 页 / 308 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9080
CMOS
Œ
y
Ž

CK
CONNECTION MEMORY TIMING
FP #2
Internal
Counter
(Read
Address)
1023
0
addresses
1
2
3
4
5
Data Output
D0o-D15o
1022
1023
0
1
2
3
4
DATA MEMORY TIMING
Data Output
D0o-D15o
1021
1022
1023
addresses
0
1
2
3
FP #1
Internal Counter
(Write Address)
1021
1022
1023
0
1
2
Data In
D0i-D15i
1021
1022
1023
0
1
2
SMX #1 Data Input/Output Frame Boundary
Note 1: Address is latched into the Data Memory by the first positive clock edge in a timeslot (edge
Œ
for Ch. 0). Data will be
clocked out by the first positive clock edge in the next timeslot (edge
y
for Ch. 0).
Note 2: Data is latched into the Data Memory by the first rising edge in a timeslot (edge
Ž
for Ch. 0) and is written into the
memory location addressed by the internal counter with the next rising edge (edge

for Ch. 0).
Figure 16 - 1024 Channel Switch Timing
ahead of time; i.e., one channel before the
addressed data is clocked out of the Data Memory. It
may be necessary to provide an external bus enable
one channel ahead of time in applications where
precharging of the external data bus is required. In
other applications where no precharge is required,
control bit from the next channel may be used in
order to ensure that the external bus is enabled at
the same time as the channel is being clocked out of
the device.
The Change Detect (CD) output of the Connection
Memory is used to interrupt the MPU. As mentioned
in the Pin and Functional descriptions, CD goes low
when the internal CRC performed by the device
indicates a change in memory contents. This feature
is particularly useful in switching applications where
the Connection Memory is configured once and is
not modified for long periods of time, e.g., in network
digital access crossconnect systems.
Any
inadvertent corruption of the memory contents will
cause CD to interrupt the processor.
D15 - D14
Unused
D13
External
Driver
Enable
D12
DM-1 or
DM-2
Select
D11
Message
Enable
D10
ODE
Control
D9 - D0
Source
Channel
Address
Figure 17 - Mapping of Address and Control Signals onto Connect Memory Data Bits
2-112