MT9075B
Preliminary Information
Bit
Name
Functional Description
Bit
Name
Functional Description
7
JAS
(0)
Jitter Attenuator Select. If one,
the attenuator may be connected to
either the transmit or receive sides
of the PCM 30 interface depend on
bit 6 - JAT/JAR. If zero, the jitter
attenuator function is disabled.
7
REDBL Receive Equalizer Auto Mode
Disable. If one, the receive
equalizer is turned off from the auto
mode. If zero, the receive equalizer
is turned on and will compensate for
loop length automatically.
(0)
6
5
JAT/JAR Transmit or Receive Jitter
Attenuator. If one, the jitter
6
5
REMID Receive Equalization Mid-range.
(0)
attenuator will function on the
transmit data. If zero, the jitter
attenuator will function on the
receive data.
If one and REDBL is one, the one-
stage equalization is enabled, which
provides approximately 6 dB of
gain. If zero, REDBL or REMAX will
control the receive equalization.
(0)
JFC
(0)
Jitter Attenuator FIFO Centre.
When this bit is toggled the read
pointer of the jitter attenuator shall
be centered. During centering the
jitter in the JA outputs is increased
by 0.0625 U.I
REMAX Receive Equalization Maximum. If
one, REDBL is one and REMID is
zero, the two-stage equalization is
(0)
enabled,
which
provides
approximately 12 dB of gain. If zero,
REDBL or REMID will control the
receive equalization.
4 - 2 JFD2- Jitter Attenuator FIFO Depth
JFD0
Control Bits. These bits determine
the depth of the jitter attenuator
FIFO as shown below:
(00)
4 - 0
---
Unused.
JFD2 JFD1 JFD0
Depth
(words)
Table 31 - Receive Equalization Control Word
(Page 02H, Address 19H)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
Bit
Name
Functional Description
48
7
6
--
64
CPLA6 Sign bit. Normalized to a positive
going one, when CPLAt6 is one
80
(0)
then the CPLA0-CPLA5 coefficient
corresponds to a positive level.
When CPLA6 is zero the coefficient
is taken to indicate a negative level.
96
112
128
5 - 0 CPLA5- Pulse shape coefficient for the first
CPLA0 time slot (within one bit cell). CPLA5
1
0
JACL Jitter Attenuator Clear bit. If one,
is the MSB.
the Jitter Attenuator, its FIFO and
(000000)
(0)
status are reset. The status
registers will identify the FIFO as
being empty. However, the actual
bit values of the data in the JA
FIFO will not be reset.
Table 32 - Custom Pulse Level 1
(Page 2, Address 1CH)
---
Unused.
Table 30 - Jitter Attenuator Control Word
(Page 02H, Address 18H)
40
MITEL [ MITEL NETWORKS CORPORATION ]
