MT9075B
Preliminary Information
single error events, which is a maximum rate of twice
per CRC-4 multiframe.
If the control bit ADSEQ is zero any combination of
receive channels may be connected to the PRBS
decoder (2 -1). Each error in the incoming
15
sequence causes the PRBS error counter to
increment. The receive channels are selected by
setting bit 2 (RRST) in the Per Time Slot Control
Word.
There is a maskable interrupts associated with the
CRC error measurement. CRCI (page 01H, address
1CH) is initiated when the least significant bit of the
counter toggles, and CRCO (page 01H, address
1DH) is initiated when the counter overflows.
If the PRBS testing is performed in a metallic or
external looparound the Per Time Slot Control Words
with TTST (transmit test, bit 3) set should have
RRST (receive test, bit 2) set at the same time.
Error Insertion
Six types of error conditions can be inserted into the
transmit PCM 30 data stream through control bits,
which are located on page 02H, address 10H. These
error events include the bipolar violation errors
(BPVE), CRC-4 errors (CRCE), FAS errors (FASE),
NFAS errors (NFSE), payload (PERR) and a loss of
signal error (LOSE). The LOSE function overrides
the HDB3 encoding function.
A-law Milliwatt
If the control bit ADSEQ is one (from master control
page 02H - access control word), the A-law digital
milliwatt sequence (Table 10), defined by G.711, is
available to be transmit on any combination of
selected channels. The channels are selected by
setting bit 3 (TTST), in the Per Time Slot Control
Word.
Per Time Slot Control
There are two per time slot control pages (page 07H
and 08H) occupying a total of 32 unique addresses.
Each address controls a matching timeslot on the 32
transmit channels (onto the line) and the equivalent
channel data on the receive (DSTo) data. For
example, address 0 of the first per time slot control
page contains program control for transmit timeslot 0
and DSTo channel 0.
The same sequence is available to replace received
data on any combination of DSTo channels. This is
accomplished by setting bit 2 (RRST) in the Per Time
Slot Control Word for the corresponding channel.
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
Per Time Slot Looping
Any channel or combination of channels may be
looped from transmit (sourced from DSTi) to receive
(output on DSTo) STBUS channels. When bit 4
(LTSL) in the Per Time Slot Control Word is set the
data from the equivalent transmit timeslot is looped
back onto the equivalent receive channel.
Any channel or combination of channels may be
looped from receive (sourced from the line data) to
transmit (output onto the line) channels. When bit 5
(RTSL) in the Per Time Slot Control Word is set the
data from the equivalent receive timeslot is looped
back onto the equivalent transmit channel.
Table 10 - A-Law Digital Milliwatt Pattern
Message Mode
The transmit data on any of the transmit channels
may be sourced either from the equivalent DSTi
channel or from a dual port RAM programmed by the
microport. The address of each dual port RAM
memory location is uniquely associated with a
transmit channel number. When bit 7 (TXMSG) in the
Per Time Slot Control Word for that channel is set
the transmit data for the channel is sourced from
within the transmit message page dual port RAM (on
page 0FH and 10H).
PRBS Testing
If the control bit ADSEQ is zero (from master control
page 02H address 13H - Access Control Word), any
channel or combination of transmit channels may be
programmed to contain a generated pseudo random
15
bit sequence (2 -1). The channels are selected by
setting bit 3 (TTST) in the Per Time Slot Control
Word.
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