Advance Information
MT9074
Bit
Name
Functional Description
Synchronization Interrupt
Mask. When unmasked (SYNI=1)
an interrupt is initiated whenever
change of state of basic frame
synchronization condition exists.
If 1 - unmasked, 0 - masked.
Bit
Name
Functional Description
7
SYNIM
7
RST
Reset. When this bit is changed
from zero to one the device will
reset to its default mode. See the
Reset Operation section for the
default settings.
6
5
SPND Suspend Interrupts. If one, the
IRQ output (pin 12 in PLCC, 85 in
MQFP) will be in a high-impedance
state and all interrupts will be
ignored. If zero, the IRQ output will
function normally.
6
5
MFSYIM Multiframe
Synchronization
Interrupt Mask. When unmasked
(MFSYI=1), an interrupt is
initiated whenever a change of
state of multiframe synchro-
nization is lost. If 1 - unmasked, 0
- masked.
INTA
Interrupt Acknowledge. A zero-to-
one or one-to-zero transition will
clear any pending interrupt and
make IRQ high impedance.
CSYNIM CRC-4
Synchronization
Mask. When
Multiframe
Interrupt
unmasked
(CSYNI=1), an interrupt is
initiated whenever a change of
4
3
CNTCLR Counter Clear. If one, all status
counters are cleared and held low.
Zero for normal operation.
state of
CRC-4 multiframe
synchronization exists. If 1 -
unmasked, 0 - masked.
SAMPLE One Second Sample. Setting this
bit causes the error counters
(change of frame alignment, loss of
frame alignment, bpv errors, crc
errors, severely errored frame
events and multiframes out of sync)
to be updated on one second
intervals coincident with the one
4
3
AISIM
Alarm
Indication
Signal
Interrupt Mask. When unmasked
(AISI=1) a change of state of
received AIS will initiate an
interrupt. If 1 - unmasked, 0 -
masked.
LOSIM
Loss of Signal Interrupt Mask.
When unmasked this interrupt bit
goes high whenever a change of
state of loss of signal (either
analog - received signal 20 or 40
dB below nominal or digital - 192
second timer (status page
address 12H bit 7).
3
2
EXTOSC External Oscillator Select. Setting
this bit connects the pin OSC1 to a
TTL compatible input. This allows
for a system design employing a
TTL output oscillator as a 20.000
Mhz reference clock.
consecutive
0’s
received)
condition exists. If 1 - unmasked,
0 - masked.
2
CEFIM
Consecutively Errored FASs
Interrupt Mask. When unmasked
an interrupt is initiated when two
1
0
RSV
Reserved. Must be kept at 0 for
normal operation.
- - -
Unused.
consecutive
errored
frame
alignment signals are received. If
1 - unmasked, 0 - masked.
Table 89 - Signalling Control Word (E1)
(Page 1, Address 1AH)
Table 90 - Interrupt Mask Word Zero (E1)
(Page 1, Address 1BH)
75
MITEL [ MITEL NETWORKS CORPORATION ]
