MT9074
Advance Information
Pin Description
Pin #
Name
LOS
Description
68Pin 100 Pin
PLCC MQFP
61
57
Loss of signal or synchronization (Output).When high, and LOS/LOF (page
02H address 13H bit 2) is zero, this signal indicates that the receive portion of the
MT9074 is either not detecting an incoming signal (bit LLOS on page 03H address
18H is one) or is detecting a loss of basic frame alignment condition (bit SYNC on
page 03H address 10H is one). If LOS/LOF=1, a high on this pin indicates a loss of
signal condition.
62
58
59
60
61
IC
NC
IC
Internal Connection. Tie to Vss (Ground) for normal operation.
No Connection. Leave open for normal operation.
63
64
Internal Connection. Tie to V (Ground) for normal operation.
SS
TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated
2.048 Mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 kHz. The transmit data
link data (TxDL) is clocked in on the rising edge of TxDLCLK. TxDLCLK can also
be used to clock DL data out of an external serial controller.
65
66
62
63
TxDL
Transmit Data Link (Input). An input serial stream of transmit data link data at 4,
8, 12, 16 or 20 kbit/s.
S/FR/C1.5i Sychronous/Freerun Extracted Clock (Input): If low, and the internal LIU is
enabled, the MT9074 is in free run mode. Pins 45 C4b and 46 F0b are outputs
generating system clocks. Slips will occur in the receive slip buffer as a result of
any deviation between the MT9074's internal PLL (which is free - running) and the
frequency of the incoming line data. If high, and the internal LIU is enabled, the
MT9074 is in Bus or Line Synchronization mode depending on the BS/LS pin. If
the internal LIU is disabled, in digital framer mode, this pin (C1.5i) takes an input
clock 1.544Mhz (T1) / 2.048Mhz (E1) that clocks in the received digital data on
pins RTIP and RRING with its rising edge.
67
68
64
65
VDD
VSS
Positive Power Supply (Input). Digital supply (+5V ± 5%).
Negative Power Supply (Input). Digital ground.
DS1 (T1 mode) or PCM 30 (E1 mode) transformer-
Device Overview
isolated four wire line. The transmit portion of the
MT9074 LIU consists of a digital buffer, a digital-to-
analog converter, and a differential line driver. The
receiver portion of the MT9074 LIU consists of an
input signal peak detector, an optional equalizer, a
smoothing filter, data and clock slicers and a clock
extractor.
The MT9074 in T1 mode operates as an advanced
T1 framer with an on-chip Line Interface Unit (LIU)
that meets or supports the recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T.403 and T.408.
The MT9074 in E1 mode operates as an advanced
PCM 30 framer with an on-chip Line Interface Unit
(LIU) that meets or supports the latest ITU-T
Recommendations for PCM 30 and ISDN primary
rate including G.703, G.704, G.706, G.775, G.796,
G.732, G.823 and I.431. It also meets or supports
the layer 1 requirements of ETSI ETS 300 011, ETS
300 166, ETS 300 233 and BS6450.
System timing may be slaved to the line, operated in
free-run mode or controlled by an external timing
source. In T1 mode the MT9074 contains a PLL
which always generates the transmit timing for the
LIU. In E1 mode the LIU also contains a Jitter
Attenuator (JA), which can be included in either the
transmit or receive path. The MT9074 will attenuate
jitter from 2.5 Hz and roll-off at a rate of 20 dB/
decade. The intrinsic jitter is less than 0.02 UI. The
PLL output (@1.544 MHz for T1 mode and @2.048
MHz for E1 mode) clocks out the transmit line data.
The Line Interface Unit (LIU) of the MT9074
interfaces the digital framer functions to either the
6
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