MT9074
Advance Information
attenuated by up to 36 dB @ 1024 kHz (translates to
2000 m. of PIC 0.65mm or 22 AWG cable) and
tolerate jitter to the maximum specified by ETS 300
011 (Figure 4).
produce an analog signal, which is passed to the
complementary line drivers.
The complementary line drivers are designed to
drive a 1:2 step-up transformer (see Figure 5 for T1
mode and Figure 6 for E1 mode). A 0.68 uF
capacitor is required between the TTIP and the
transmit transformer. Resistors RT (as shown in
Figure 5) are for termination for transmit return loss.
The values of RT may be optimized for T1 mode, E1
120Ω lines, E1 75Ω lines or set at a compromise
value to serve multiple applications. Program the LIU
Control Word (address 1FH page 1) to adjust the
pulse amplitude accordingly.
The LOS output pin function is user selectable to
indicate any combination of loss of signal and/or loss
of basic frame synchronization condition.
The LLOS (Loss of Signal) status bit indicates when
the receive signal level is lower than the analog
threshold for at least 1 millisecond, or when more
than 192 consecutive zeros have been received. In
E1 mode the analog threshold is either of -20 dB or -
40 dB. For T1 mode the analog threshold is -40 dB.
Alternatively, the pulse level and shape may be
discretely programmed by writing to the Custom
Pulse Level registers (addresses 1CH to 1FH, page
2) and setting the Custom Transmit Pulse bit high (bit
3 of the Transmit Pulse Control Word). In this case
the output of each of the registers directly drives the
D/A converter going to the line driver. Tables 1 and 2
show recommended transmit pulse amplitude
settings.
In T1 mode, the receive LIU circuit requires a
terminating resistor of 100Ω across the device side
of the receive 1:1 transformer.
In E1 mode the receive LIU circuit requires a
terminating resistor of either 120Ω or 75Ω across the
device side of the receive1:1 transformer.
The jitter tolerance of the clock extractor circuit
exceeds the requirements of TR 62411 in T1 mode
(see Figure 3) and G.823 in E1 mode (see Figure 4).
In T1 mode, the template for the transmitted pulse
(the DSX-1 template) is shown in Figure 7. The
nominal peak voltage of a mark is 3 volts. The ratio
of the amplitude of the transmit pulses generated by
TTIP and TRING lie between 0.95 and 1.05.
Transmitter
The transmit portion of the MT9074 LIU consists of a
high speed digital-to-analog converter and
complementary line drivers.
In E1 mode, the template for the transmitted pulse,
as specified in G.703, is shown in Figure 8. The
nominal peak voltage of a mark is 3 volts for 120 Ω
twisted pair applications and 2.37 volts for 75 Ω coax
applications. The ratio of the amplitude of the
transmit pulses generated by TTIP and TRING lie
between 0.95 and 1.05.
When a pulse is to be transmitted, a sequence of
digital values (dependent on transmit equalization)
are read out of a ROM by a high speed clock. These
values drive the digital-to-analog converter to
Peak to Peak
Jitter Amplitude
(log scale)
138UI
100UI
28UI
10UI
1.0UI
0.4UI
Jitter Frequency
(log scale)
100Hz
10Hz
4.9Hz
1.0kHz 10kHz 100kHz
0.1Hz 1.0Hz
Figure 3 - Input Jitter Tolerance as Recommended by TR-62411 (T1)
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