Advance Information
MT9074
After power-up, the basic frame alignment framer will
search for a frame alignment signal (FAS) in the
PCM 30 receive bit stream. Once the FAS is
detected, the corresponding bit 2 of the non-frame
alignment signal (NFAS) is checked. If bit 2 of the
NFAS is zero a new search for basic frame alignment
is initiated. If bit 2 of the NFAS is one and the next
FAS is correct, the algorithm declares that basic
frame synchronization has been found (i.e., page
03H, address 10H, bit 7, SYNC is zero).
3) Manual re-framing of the receive basic frame
alignment and signalling multiframe alignment functi-
ons can be performed at any time.
4) The transmit RAI bit will be one until basic frame
alignment is established, then it will be zero.
5) E-bits can be optionally set to zero until the
equipment interworking relationship is established.
When this has been determined one of the following
will take place:
Once basic frame alignment is acquired the
signalling and CRC-4 multiframe searches will be
initiated. The signalling multiframe algorithm will
align to the first multiframe alignment signal pattern
(MFAS = 0000) it receives in the most significant
nibble of channel 16 (page 3, address 10H, bit 6,
MFSYNC = 0). Signalling multiframing will be lost
when two consecutive multiframes are received in
error.
a) CRC-to-non-CRC operation - E-bits = 0,
b) CRC-to-CRC operation - E-bits as per G.704 and
I.431.
6) All manual re-frames and new basic frame
alignment searches start after the current frame
alignment signal position.
7) After basic frame alignment has been achieved,
loss of frame alignment will occur any time three
consecutive incorrect basic frame alignment signals
are received. Loss of basic frame alignment will reset
the complete framing algorithm.
The CRC-4 multiframe alignment signal is a 001011
bit sequence that appears in PCM 30 bit position one
of the NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table
9). In order to achieved CRC-4 synchronization two
consecutive CRC-4 multiframe alignment signals
must be received without error (page 03H, address
10H CRCSYN = 0).
8) When CRC-4 multiframing has been achieved, the
primary basic frame alignment and resulting
multiframe alignment will be adjusted to the basic
frame alignment determined during CRC-4
synchronization. Therefore, the primary basic frame
alignment will not be updated during the CRC-4
multiframing search, but will be updated when the
CRC-4 multiframing search is complete.
The E1 framing algorithm supports automatic
interworking of interfaces with and without CRC-4
processing capabilities. That is, if an interface with
CRC-4 capability, achieves valid basic frame
alignment, but does not achieve CRC-4 multiframe
alignment by the end of a predefined period, the
distant end is considered to be a non-CRC-4
interface. When the distant end is a non-CRC-4
interface, the near end automatically suspends
receive CRC-4 functions, continues to transmit CRC-
4 data to the distant end with its E-bits set to zero,
and provides a status indication. Naturally, if the
distant end initially achieves CRC-4 synchronization,
CRC-4 processing will be carried out by both ends.
This feature is selected when control bit AUTC (page
01H, address 10H) is set to zero.
Reframe
E1 Mode
The MT9074 will automatically force a reframe, if
three consecutive frame alignment patterns or three
consecutive non-frame alignment bits are in error.
T1 Mode
The MT9074 will automatically force a reframe if the
framing bit error density exceeds the threshold
programmed by control bits RS1-0 (Framing Mode
Select Word page 1H, address 10H). RS1 = RS0 = 0
forces a reframe for 2 errors out of a sliding window
of 4 framing bits. RS1 = 0, RS0 = 1 forces a reframe
with 2 errors out of 5. RS1 = 1, RS0 = 0 forces a
reframe with 2 errors out of 6. RS1 = RS0 = 1
disables the automatic reframe.
Notes for Synchronization State Diagram
(Figure 15)
1) The basic frame alignment, signalling multiframe
alignment, and CRC-4 multiframe alignment
functions operate in parallel and are independent.
2) The receive channel associated signalling bits and
signalling multiframe alignment bit will be frozen
when multiframe alignment is lost.
In ESF mode all framing bits are checked. In D4
mode either Ft bits only (if control bit 2 - FSI - of
Framing Mode Select Register is set low) or Ft and
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