Advance Information
MT9074
Data Link Operation in T1 mode
Data Link Operation
SLC-96 and ESF protocol allow for carrier messages
to be embedded in the overhead bit position. The
MT9074 provides 3 separate means of controlling
these data links. See Data Link and Rx Equalization
Control Word - address 12H, page 1H.
Data Link Operation in E1 mode
In E1 mode MT9074 has a user defined 4, 8, 12, 16
or 20 kbit/s data link for transport of maintenance
and performance monitoring information across the
PCM 30 link. This channel functions using the S bits
a
• The data links (transmit and receive) may be
sourced (sunk) from an external controller using
dedicated pins on the MT9074 in T1 mode (enabled
by setting the bit 7 - EDL of the Data link Control
Word).
(S ~S ) of the PCM 30 timeslot zero non-frame
a4
a8
alignment signal (NFAS). Since the NFAS is
transmitted every other frame - a periodicity of 250
microseconds - the aggregate bit rate is a multiple of
4 kb/s. As there are five S bits independently
a
available for this data link, the bit rate will be 4, 8, 12,
16 or 20 kb/s, depending on the bits selected for the
Data Link (DL).
• Bit - Oriented Messages may be transmit and
received via a dedicated TxBOM register (page 1H,
address 13H) and a RxBOM (page 3H, address
15H). Transmission is enabled by setting bit 6 -
BIOMEn in the Data link Control Word. Bit - oriented
messages may be periodically interrupted (up to
once per second) for a duration of up to 100
milliseconds. This is to accommodate bursts of
message - oriented protocols. See Table 16 for
message structure.
The S bits used for the DL are selected by setting
a
the appropriate bits, S ~S , to one in the Data Link
a4
a8
Select Word (page 01H, address 17H, bits 4-0).
Access to the DL is provided by pins TxDLCLK,
TxDL, RxDLCLK and RxDL, which allow easy
interfacing to an external controller.
Data to be transmit onto the line in the Sa bit position
is clocked in from the TxDL pad (pin 65 in PLCC, pin
62 in MQFP) with the clock TxDLCLK (pin 64 in
PLCC, pin 61 in MQFP). Although the aggregate
clock rate equals the bit rate, it has a nominal pulse
width of 244 ns, and it clocks in the TxDL as if it were
a 2.048 Mb/s data stream. The clock can only be
active during bit times 4 to 0 of the STBUS frame.
The TxDL input signal is clocked into the MT9074 by
the rising edge of TxDLCLK. If bits are selected to be
a part of the DL, all other programmed functions for
those Sa bit positions are overridden.
• An internal HDLC controller may be attached to the
data link.
External Data Link
In T1 mode MT9074 has two pairs of pins (TxDL and
TxDLCLK, RxDL and RxDLCLK) dedicated to
transmitting and receiving bits in the selected
overhead bit positions. Pins TxDLCLK and RxDLCLK
are clock outputs available for clocking data into the
MT9074 (for transmit) or external device (for receive
information). Each clock operates at 4 Khz. In the
SLC-96 mode the optional serial data link is
multiplexed into the Fs bit position. In the ESF mode
the serial data link is multiplexed into odd frames, i.e.
the FDL bit positions.
The RxDLCLK signal (pin 39 in PLCC, pin 20 in
MQFP) is derived from the receive extracted clock
and is aligned with the receive data link output RxDL.
The HDB3 decoded receive data, at 2.048 Mbit/s, is
clocked out of the device on pin RxDL (pin 40 in
PLCC, pin 21 in MQFP). In order to facilitate the
attachment of this data stream to a Data Link
controller, the clock signal RxDLCLK consists of
positive pulses, of nominal width of 244 ns, during
the Sa bit cell times that are selected for the data
link. Again, this selection is made by programming
address 17H of master control page 01H. No DL
data will be lost or repeated when a receive frame
slip occurs. See the AC Electrical Characteristics for
timing requirements.
Bit - Oriented Messaging
In T1 mode MT9074 Bit oriented messaging may be
selected by setting bit 6 (BIOMEn) in the Data Link
Control Word (page 1H, address 12H). The transmit
data link will contain the repeating serial data stream
111111110xxxxxx0 where the byte 0xxxxxx0
originates from the user programmed register
"Transmit Bit Oriented Message" - page 1H address
13H. The receive BIOM register "Receive Bit
Oriented Message" - page 3H, address 15H, will
contain the last received valid message (the
0xxxxxx0 portion of the incoming serial bit stream).
To prevent spurious inputs from creating false
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