Advance Information
MT9074
G.704 and G.732 for more details on CAS
multiframing requirements.
MT9074 Access and Control
The Control Port Interface
A CAS signalling multiframe consists of 16 basic
frames (numbered 0 to 15), which results in a
multiframe repetition rate of 2 msec. It should be
noted that the boundaries of the signalling
multiframe may be completely distinct from those of
the CRC-4 multiframe. CAS multiframe alignment is
based on a multiframe alignment signal (a 0000 bit
sequence), which occurs in the most significant
nibble of time slot 16 of basic frame 0 of the CAS
multiframe. Bit 6 of this time slot is the multiframe
alarm bit (usually designated Y). When CAS
multiframing is acquired on the receive side, the
transmit Y-bit is zero; when CAS multiframing is not
acquired, the transmit Y-bit is one. Bits 5, 7 and 8
(usually designated X) are spare bits and are
normally set to one if not used.
The control and status of the MT9074 is achieved
through a non-multiplexed parallel microprocessor
port. The parallel port may be configured for
Motorola style control signals (by setting pin INT/
MOT low) or Intel style control signals (by setting pin
INT/MOT high).
Control and Status Register Access
The controlling microprocessor gains access to
specific registers of the MT9074 through a two step
process. First, writing to the Command/Address
Register (CAR) selects one of the 15 pages of
control and status registers (CAR address: AC4 = 0,
AC3-AC0 = don't care, CAR data D7 - D0 = page
number). Second, each page has a maximum of 16
registers that are addressed on a read or write to a
non-CAR address (non-CAR: address AC4 = 1, AC3-
AC0 = register address, D7-D0 = data). Once a page
of memory is selected, it is only necessary to write to
the CAR when a different page is to be accessed.
See the AC Electrical Characteristics section.
Time slot 16 of the remaining 15 basic frames of the
CAS multiframe (i.e., basic frames 1 to 15) are
reserved for the ABCD signalling bits for the 30
payload channels. The most significant nibbles are
reserved for channels 1 to 15 and the least
significant nibbles are reserved for channels 16 to
30. That is, time slot 16 of basic frame 1 has ABCD
for channel 1 and 16, time slot 16 of basic frame 2
has ABCD for channel 2 and 17, through to time slot
16 of basic frame 15 has ABCD for channel 15 and
30.
Please note that for microprocessors with read/write
cycles less than 200 ns, a wait state or a dummy
operation (for
C
programming) between two
Page Address
Processor
Access
ST-BUS
Access
Register Description
D7 - D0
00000001 (01H)
00000010 (02H)
00000011 (03H)
00000100 (04H)
00000101 (05H)
00000110 (06H)
00000111 (07H)
00001000 (08H)
00001001 (09H)
00001010 (0AH)
00001011 (0BH)
00001011 (0CH)
Master
Control
R/W
R/W
R
- - -
Master
Status
- - -
R/W
R/W
R/W
Per Channel Transmit Signalling
Per Channel Transmit Signalling
Per Time Slot Control
CSTi
CSTi
- - -
Per Time Slot Control
R/W
R/W
R/W
R/W
R/W
- - -
Per Channel Receive Signalling
Per Channel Receive Signalling
HDLC0 Control and Status
HDLC1 Control and Status
CSTo
CSTo
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Table 13 - Page Summary
19
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