MT90732
CMOS
RNIB2/TDOUT
RNIB0/TFOUT
RNIB3/RSD
RNIB1/TCG
RCK/RCKL
Advance Information
RNC/RSC
RNF/RSF
62
RP/RDL
RLOC
RLOF
RAIS
GND
ROD
VDD
RN
CV
RCG
61
10
68
67
66
65
64
ROC
ROF
FE
NRZLINE
BIP-4
M0
M1
VDD
GND
MICRO
SER
TLBK
PLBK
TAIS
LPT
TLOC
FORCEFE
27
63
9
8
7
6
5
4
3
2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
BIP-4E
XNC/TCOUT
XNF
XCK
XNIB0/XSD
XNIB1/TCIN
XNIB2
XNIB3/XSF
GND
VDD
TLCINV
DAIS
RDY
WR
RD
ALE
SEL
44
TCK/TCKL
TP/TDL
AD7
AD6
AD5
AD4
AD3
AD2
AD1
TOD
TOC
GND
RESET
Figure 2 - Pin Connections
Pin Description
Power Supply and Ground
Pin #
1,17,35,51
18,34,52,68
Name
VDD
GND
I/O/P
P
P
Description
VDD.
5-volt supply voltage, +/- 5%
Ground.
Note: I = Input; O = Output; P = Power
Line Side Receive
Pin #
2
3
4
Name
RP/RDL
RN
RCK/RCKL
I/O/P
I
I
I
Description
Receive Positive Rail/Receive NRZ Data.
Receive positive rail/NRZ data
generated from line interface circuit.
Receive Negative Rail Data.
Receive negative rail data generated from line
interface circuit.
Receive Clock Rail/Receive Clock NRZ.
The receive clock is used for clock-
ing in the rail/NRZ data signals.
Note: I = Input; O = Output; P = Power
5-16
VDD
TOF
AD0
TN
MITEL [ MITEL NETWORKS CORPORATION ]
