MT90220
Table of Contents
6.0 Support Blocks.............................................................................................................................................
6.1 Counter Block...........................................................................................................................................
6.1.1 UTOPIA Input I/F counters...............................................................................................................
6.1.2 Transmit PCM I/F Counters .............................................................................................................
6.1.3 Receive PCM I/F Counters ..............................................................................................................
6.1.4 Access to the Counters ....................................................................................................................
6.2 Interrupt Block ..........................................................................................................................................
6.2.1 IRQ Master Status and IRQ Master Enable Registers.....................................................................
6.2.2 IRQ Link Status and IRQ Link Enable Registers..............................................................................
6.2.2.1 Bit 7 and 6 of IRQ Link 0 Status and IRQ Link 0 Enable Registers ..........................................
6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA Input UNI Overflow Status Registers .............................
6.2.4 IRQ IMA Group Overflow Status and Enable Registers...................................................................
6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers ..............
6.3 Register and Memory Map .......................................................................................................................
6.3.1 Access to the Various Registers ......................................................................................................
6.3.2 Direct Access ...................................................................................................................................
6.3.3 Indirect Access.................................................................................................................................
6.3.4 Clearing of Status Bits......................................................................................................................
6.3.4.1 Toggle Bit ..................................................................................................................................
6.3.5 Test Modes ......................................................................................................................................
33
33
33
33
33
33
34
34
35
35
36
36
36
36
36
37
37
37
37
37
7.0 Register Descriptions ..................................................................................................................................
7.1 Utopia Register Description......................................................................................................................
7.2 TX Registers Description..........................................................................................................................
7.3 TX ICP Register Description ....................................................................................................................
7.4 RX Registers Description .........................................................................................................................
7.5 RX ICP Cell Registers Description ...........................................................................................................
7.6 External SRAM Register Description .......................................................................................................
7.7 RX Delay Registers Description ...............................................................................................................
7.8 RX Recombiner Registers Description .....................................................................................................
7.9 TX/RX and PLL Control Registers Description.........................................................................................
7.10 Counter Registers Description ................................................................................................................
7.11Interrupt Registers Description .................................................................................................................
7.12 Miscellaneous Registers Description ......................................................................................................
38
41
45
50
52
57
60
62
65
67
73
75
78
8.0 Application Notes......................................................................................................................................... 79
8.1 Connecting the MT90220 to Various T1/E1 Framers ............................................................................... 79
9.0 AC/DC Characteristics................................................................................................................................. 85
iii
MITEL [ MITEL NETWORKS CORPORATION ]
