MT90220
Applications
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Cost effective single chip solution to implement
IMA and UNI links over T1 or E1 in all public or
private UNI, NNI and B-ICI applications
ATM Edge switch IMA and UNI Line Card
Design
Can be used for cost reduction in current
applications based on FPGA implementation
Hardware functions that are implemented in the
MT90220 device are:
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Utopia Level 2 PHY Interface
Incoming HEC verification and correction
(optional),
Generation of a new HEC byte
Format outgoing bytes into multi-vendor PCM
formats
Retrieve ATM Cells from the incoming multi-
vendor PCM format
Perform cell delineation
Provide various counters to assist in
performance monitoring
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Description
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The MT90220 device is targeted to systems
implementing the ATM FORUM UNI specifications for
T1/E1 rates or Inverse Multiplexing for ATM (IMA). In
the MT90220 architecture, up to 8 physical and
independent T1/E1 streams can be terminated
through the utilization of off-the-shelf, traditional T1/
E1 framers and LIUs. This allows ATM designers to
leverage previous T1/E1 design experience,
hardware and software implementation, and to select
the best T1/E1 framer for the required application.
The MT90220 device provides ATM system
designers with a flexible architecture when
implementing ATM access over existing and
deployed trunk interfaces, allowing a migration
towards ATM service technology. In addition to
allowing for the design of ATM UNI specifications for
T1/E1 rates, the MT90220 device is compliant with
the ATM FORUM IMA specifications for controlling
IMA groups of up to 8 trunks in a single chip. The
MT90220 can be configured to operate in different
modes to facilitate the implementation of the IMA
function at both CPE and Central Office sites. For
systems targeting ATM over T1/E1 with IMA and UNI
operating simultaneously, the MT90220 device
provides the ideal architecture and capabilities.
The device provides up to 4 internal IMA circuits and
allows for bandwidth scaleability through the use of
the UTOPIA MPHY, Level 2 specification at 25Mhz.
The implementation of the IMA as per AF-PHY-
0086.001 Inverse Multiplexing for ATM (IMA)
Specification Version 1.1 is divided into hardware
and software functions. Hardware functions are
implemented in the MT90220 device and software
functions are implemented by the user. Additional
hardware functions are included to assist in the
collection of statistical information to support MIB
implementation.
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Hardware functions that are implemented by the IMA
processor in the MT90220 device are:
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Transmit scheduler (one per IMA group)
Generation of the TX IMA Data Cell Rate
Generation and insertion of ICP cells, Filler
Cells and Stuff Cells in IMA mode and Idle Cells
in UNI (non-IMA) mode; the ICP cells are
programmed by the user and the Filler and Idle
cells are pre-defined
Retrieve and process ICP cells in IMA Mode
Perform IMA Frame synchronization
Management of RX links to be part of the
internal re-sequencer when active
Extraction of RX IMA Data Cell Rate
Verification of delays between links
Perform re-sequencing of ATM cells using
external asynchronous Static RAM
Can accommodate more than 400 msec of link
differential delay depending on the amount of
external memory
Provide structured Interrupt scheme to report
various events.
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MITEL [ MITEL NETWORKS CORPORATION ]
