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MT90210 参数 Datasheet PDF下载

MT90210图片预览
型号: MT90210
PDF下载: 下载PDF文件 查看货源
内容描述: 多速率并行接入电路 [Multi-Rate Parallel Access Circuit]
分类和应用:
文件页数/大小: 27 页 / 136 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT90210
Preliminary Information
A6
A7
VSS
A8
A9
VDD
A10
VSS
A11
A12
RBC
VDD
VSS
WBC
S0
S1
S2
VSS
VDD
S3
80
82
A5
VSS
VDD
A4
A3
A2
VSS
A1
A0
VDD
Strobe
VSS
P7
P6
P5
VSS
P4
VDD
P3
P2
VSS
P1
P0
R/W2
R/W1
VDD2
CKout
PCLK
RST
PLLVDD
78
76
74
72
70
68
66
64
62
60
58
56
54
52 50
48
84
46
86
44
88
42
90
92
94
36
96
34
98
32
100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
40
38
100 PIN PQFP
PLLAGND
LP1
LP2
PLLVSS
IDDTN
TD
VSS2
C16-
C16+
VDD2
MD0
MD1
MD2
F0i
TRST
TCK
TMS
TDI
HC4
SCLK
Note: the PQFP package meets the JEDEC standard MO-108, CC1.
Critical dimensions:
Lead pitch = 0.65mm,
Body Size = 14mm x 20mm,
Package size = 17.9mm x 23.9mm.
Pin Description
Pin
95-97,
100,
1-3,
6
7-9,
11-15
18-22,
24-26
27
29
30
Name
S0-S2,
S3,
S4-S6,
S7
S8-S10,
S11-S15
S16-S20
S21-S23
TDO
RDin
OEser
Description
Serial Lines 0-7
(TTL compatible with internal pullups in the range 25 - 125kΩ).
Bidirectional, time division multiplexed serial streams. According to mode selected by
MD0-2 inputs, distinct data rates can be selected at the serial port. In mode 3, these lines
are configured as inputs only. In modes 1, 2, 4 and 5, these lines become bidirectional.
Serial Lines 8-15.
See description for S0-S7 above. In mode 3, S8-S11 are inputs and
S12-S15 are outputs. In modes 1, 2, 4 and 5 these are bidirectional lines.
Serial Lines 16-23.
See descripton for S0 - S7 above. For mode 3, these lines are outputs
and operate at 8.192 Mb/s rates. When operating in modes 1, 2, 4 and 5, these lines are
bidirectional.
Boundary Scan Test Data Output.
Read P0-P7 input clock.
This input is used by the MT90210 to sample bytes coming in at
the parallel port P0-P7 lines. Typically, the user should connect CKout to this input.
Serial Port Output Enable (Input).
On the parallel-to serial conversion direction, this input
is used by the MT90210 to know which time-slots on the serial output streams will be
placed in high-impedance. This input is sampled synchronously along with the parallel
input data before the parallel-to-serial conversion takes place. When low, output serial
channels are actively driven. When set high, the output bus drivers are disabled.
2-146
S4
S5
S6
VDD
VSS
S7
S8
S9
S10
VSS
S11
S12
S13
S14
S15
VDD
VSS
S16
S17
S18
S19
S20
VSS
S21
S22
S23
TDO
VSS2
RDin
OEser
Figure 2 - Pin Connections