Advance Information
Pin Description (continued)
Pin #
44
48
PLCC SSOP
12
12,36
13
Name
Description
MT89L86
V
DD
RESET
+3.3 Volt Power Supply.
Device Reset
( 5v-tolerant input). This pin is only available for the 48-pin SSOP
package. In normal operation, This active low input puts the MT89L86 in its reset state.
It clears the internal counters and registers. All ST-BUS outputs are set to the high
impedance state. The RESET pin must be held low for a minimum of 100nsec to reset
the device.
Frame Pulse
(5V-tolerant Input). This input accepts and automatically identifies frame
synchronization signals formatted according to ST-BUS and GCI interface
specifications.
Clock
(5V-tolerant Input). Serial clock for shifting data in/out on the serial streams.
Depending on the serial interface speed selected by IMS (Interface Mode Select)
register, the clock at this pin can be 4.096 or 8.192 MHz.
13
14
FR
14
15
CLK
15-17 16-18
STi8/A0,
Address 0-2 / Input Streams 8-10
(5V-tolerant Input). When the non-multiplexed CPU
STi9/A1, bus is selected, these lines provide the A0-A2 address lines to the MT89L86 internal
STi10/A2 registers. When the 16x8 switching configuration is selected, these pins are ST-BUS
serial inputs 8 to 10 receiving data at 2.048 Mb/s.
19-21 20-22 STi11/A3,
Address 3-5 / Input Streams 11-13
(5V-tolerant Input). When the non-multiplexed
STi12/A4, CPU bus is selected, these lines provide the A3-A5 address lines to the MT89L86
STi13/A5 internal registers. When the 16x8 switching configuration is selected, these pins are
ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s.
22
23
DS/RD
Data Strobe/Read
(5V-tolerant Input). When the non-multiplexed CPU bus or Motorola
multiplexed bus is selected, this input is DS. This active high input works in conjunction
with CS to enable read and write operation.
For the Intel/National multiplexed bus interface, this input is RD. This active low input
configures the data bus lines (AD0-7) as outputs.
23
24
R/W\WR
Read/Write \ Write
(5V-tolerant Input). For the non-multiplexed or Motorola multiplexed
bus interface, this input is R/W. This input controls the direction of the data bus lines
(AD0-AD7) during a microprocessor access.
For the Intel/National multiplexed bus interface, this input is WR. This active low signal
configures the data bus lines (AD0-7) as inputs.
CS
Chip Select
(5V-tolerant Input). This active low input enables a microprocessor read
or write of the MT89L86’s internal control register or memories.
24
26
25-27 27-29 AD7-AD0
Data Bus
(Bidirectional): These pins provide microprocessor access to the internal
29-33 31-35
control registers, connection memories high and low and data memories. For the
multiplexed bus interface these pins also provide the input address to the internal
Address Latch circuit.
34
35
1,
25,37
38
V
SS
Ground.
STo7/A7
ST-BUS Output 7/Address 7 input
(Three-state output/input). The function of this pin
is determined by the switching configuration enabled. If non-multiplexed CPU bus is
used along with data rates employing 8.192 Mb/s rates, this pin provides A7 address
input function. For 2.048 Mb/s applications or when the multiplexed CPU bus interface
is selected, this pin assumes STo7 function. See Tables 1, 2, 6 & 7 for more details.
Note that for applications where A7 input and STo7 output are required simultaneously
(e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin
STi7/A7.
3
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