MT89L86
Serial
Interface
Data Rate
2 Mb/s
2 Mb/s
2 Mb/s
Interface
Clock
required at
CLK Pin
(MHz)
4.096
4.096
4.096
Number of
Input x
Output
Streams
8x8
16x8
10x10
Matrix
Channel
Capacity
256x256 Non-Blocking
512x256 Blocking
128x128 Non-Blocking
(only 4-input x 4-output
can be selected)
Advance Information
Input/Output
Streams Used
Variable/
Constant
throughput
Delay
Selection
Yes
No
Yes
STi0-7/STo0-7
STi0-15/STo0-7
STi0-9/STo0-9
Nibble
Switching
(2 Mb/s)
4 Mb/s
4 Mb/s
8 Mb/s
4.096
8x4
512x256 Nibbles
STi0-7/STo0-3
No
4.096
4.096
8.192
8x4
4x4
2x2
512x256 Blocking
256x256 Non-Blocking
256x256 Non-Blocking
STi0-7/STo0-3
STi0-3/STo0-3
STi0-1/STo0-1
No
Yes
Yes
Table 1 - Switching Configurations for Identical Input and Output Data Rate
Different Input/Output Data Rates
When Different I/O rate is selected by the DMO bit,
the input and output data rates should be selected at
the IDR and ODR bits, respectively. The Switching
Configuration Bits (SCB) are ignored with this
operation. This selection allows the user to multiplex
conventional 2.048 Mb/s serial streams into two
higher rates and vice-versa. In addition to the rate
conversion itself, the MT89L86 allows for a complete
256 x 256 channel non-blocking switch at different
rates. In this operation, the per-channel variable/
constant throughput delay selection is provided.
Depending on which data rates are programmed for
input and output streams, the number of data
streams used on the input and output as well as the
serial interface clock (CLK input pin) is different.
Once the CPU defines the data rates at the IDR and
ODR bits, the MT89L86 automatically configures
itself with the appropriate number of input and output
Interface
Clock
required at
CLK Pin
(MHz)
4.096
8.192
4.096
streams for the desired operation. Table 2
summarizes the four options available when it is
used with different I/O rates. Figures 21 to 24 show
the timing for each of the four modes shown in Table
2.
Input Frame Offset Selection
For the 4.096 and 8.192 Mb/s serial interface data
rates, the MT89L86 provides a feature called Input
Frame Offset allowing the user to compensate for the
varying delays at the incoming serial inputs while
building large switch matrices. Usually, different
delays occur on the digital backbones causing the
data and frame synchronization signals to be skewed
at the input of the switch device. This may result in
the system frame synchronization pulse to be active
at the MT89L86’s FR input before the first bit of the
frame is received at the serial inputs.
Input and
Output
Data Rates
2 Mb/s to 4 Mb/s
2 Mb/s to 8 Mb/s
4 Mb/s to 2 Mb/s
8 Mb/s to 2 Mb/s
Number
of Input
x Output
Streams
8x4
8x2
4x8
Matrix
Channel Capacity
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
Input/Output
Streams Used
STi0-7/STo0-3
STi0-7/STo0-1
STi0-3/STo0-7
Variable/
Constant
throughput
Delay
Selection
Yes
Yes
Yes
Yes
8.192
2x8
256x256 Non-Blocking
STi0-1/STo0-7
Table 2 - Switching Configurations for Different I/O Data Rates
8
MITEL [ MITEL NETWORKS CORPORATION ]
