Advance Information
MT89L86
throughput delay is guaranteed. For such
applications, the MT89L86 allows cost effective
implementations of Non-Blocking matrices ranging
up to 1024 channels. Figures 12 and 13 show the
block diagram of implementations with Non-Blocking
capacities of 512 and 1024-channel, respectively.
8051 family of CPUs do not provide Data Ready type
of inputs, some external logic and
software
intervention have to be provided between the
MT89L86 and the 8051 microcontroller to allow read/
write operations. The external logic described in
Figure 14 is a block diagram of a logical connection
between the MT89L86 and 8051. Its main function is
to store the 8051 data during a write and the
MT89L86 data during a read.
Interfacing the MT89L86 with 8051
The Intel 8051 is a very cost effective solution for
many applications that do not require a large CPU
interaction and processing overhead. However, in
applications where 8051 is connected to peripherals
operating on a synchronous 8 kHz time-base like the
MT89L86, some connectivity issues have to be
addressed. The MT89L86 may hold the CPU read/
write cycle due to internal contention between the
on-chip microprocessor port and the internal serial-
to-parallel and parallel-to-serial converters. Since the
For a write, address is latched by the MT89L86’s
internal address latch on the falling edge of the ALE
input. Whenever a read or write operation is done to
the MT89L86, the address decoded signal (MTA) is
used to latch the state of RD, WR, and the ALE
signals, until the data acknowledge output signal is
provided by the MT89L86, releasing the latches for a
new read/write cycle. Latch U5 is used to hold the
8051 data for a write until the CPU is ready to accept
it (when DTA goes low). Latch U4 stores the
MT89L86 output data during a read cycle whenever
8 Streams
4 Streams
@2.048 Mb/s
@4.096 Mb/s
16 Streams
8 Streams
@2.048 Mb/s
MT89L86
MT89L86
@4.096 Mb/s
8
8
4
4
512 x 256
512 x 256
16
IN
OUT
IN
OUT
MT89L86
MT89L86
8
512 x 256
512 x 256
8 Streams
@2.048 Mb/s
4 Streams
@4.096 Mb/s
Figure 12 - 512-Channel Non-Blocking Switch Matrix with Serial Streams at 2.048 or 4.096 Mb/s
8
8
MT89L86
512 x 256
MT89L86
512 x 256
8 Streams
@2.048 Mb/s
16
16 Streams
@2.048 Mb/s
IN
OUT
MT89L86
512 x 256
MT89L86
512 x 256
8 Streams
@2.048 Mb/s
8
8
MT89L86
512 x 256
MT89L86
512 x 256
8 Streams
@2.048 Mb/s
16
16 Streams
@2.048 Mb/s
IN
OUT
MT89L86
512 x 256
MT89L86
512 x 256
8 Streams
@2.048 Mb/s
Figure 13 - 1024-Channel Non-Blocking Switch Matrix with Serial Streams at 2.048 Mb/s
21
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