MT8986
AC Electrical Characteristics† - Intel/National- HPC Multiplexed Bus Mode
Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
ALE pulse width
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
tALW
tADS
20
8
ns
ns
ns
ns
Address setup from ALE falling
Address hold from ALE falling
RD active after ALE falling
Data setup from DTA Low on Read
CS hold after RD/WR
tADH
tALRD
tDDR
tCSRW
tRW
9
9
10
0
ns C =150 pF
L
ns
ns
ns
RD pulse width (fast read)
CS setup from RD
80
tCSR
tDHR
tWW
0
Data hold after RD
10
50
90
90
ns C =150 pF,R =1 KΩ
L L
10 WR pulse width (fast write)
11 WR delay after ALE falling
12 CS setup from WR
ns
ns
ns
ns
ns
tALWR
tCSW
tDSW
tSWD
10
0
13 Data setup from WR (fast write)
90
14 Valid Data Delay on write
(slow write)
122
15 Data hold after WR inactive
16 Acknowledgement Delay:
tDHW
tAKD
8
ns
C =150 pF
L
Reading Data Memory
560
1220
ns
ns
ns
ns
Reading/Writing Conn. Memories
Writing to Control & Mode Reg.
Reading from Control & Mode Reg.
300/370 730/800
47
60
95
125
17 Acknowledgement Hold Time
tAKH
10
60
110
ns C =150 pF,R =1 KΩ*
L L
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
*
2-94
MITEL [ MITEL NETWORKS CORPORATION ]
