MT8986
tCK
2.0V
0.8V
CLK
(4.096 or
8.192
MHz)
tCH
tCL
tFS
tFH
2.0V
0.8V
FR
(positive)
tFW
tDD
tZA
tAZ
2.0V
0.8V
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
Ch. 63 or 127
Bit 5
STo
STi
High Z
tDS
tDH
2.0V
0.8V
B0
B7
B6
B5
2.0V
0.8V
CLK
(4.096
MHz)
tFS
tFH
FR
(negative)
2.0V
0.8V
tFW
tDD
2.0V
0.8V
Ch. 63
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
STo
STi
tDS
tDH
2.0V
0.8V
B0
B7
B6
B5
Figure 20 - Serial Interface Timng (CLKM bit=1, DMO bit=0) - 4.096 and 8.192 Mb/s
Note: For 8.192 Mb/s clock, only the positive polarity frame pulse is accepted by the MT8986 device.
2.0V
ODE
0.8V
2.4V
0.4V
STo0
to
STo9
*
*
tOED
tOED
Figure 21 - Output Driver Enable for Streams at 4.096 and 8.192 Mb/s
2-90
MITEL [ MITEL NETWORKS CORPORATION ]
