MT8986
8
RD
MTA
DTA
OE
LE
MTA
CS
MT8986
Address
Decode
8
LATCH
LATCH
RES
RST
AD0-AD7
MTA
LE
OE
8051
AD0
MT8986
Access
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
MT8986
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
D
Q
CK PR
LRD
RD
D
Q
WR
WR
RD
CS
CK PR
LWR
D
Q
DTA
CK PR
R
C
RES
DTA
Figure 14 - Interfacing the MT8986 to the 8051 Microcontroller
Enough time need to be provided between two CPU
accesses to allow the first access to complete; i.e.,
to allow for an internal MT8986 reaction over the first
RD/WR access. For a read operation, a minimum of
1220 ns have to be guaranteed between two
successive accesses. For write, at least 800 ns has
to be respected.
goes low). Latch U4 stores the MT8986 output data
during a read cycle whenever DTA goes low. When
writing to the MT8986, one write operation is
sufficient. However, when reading MT8986, two read
operations with the same address are required, with
the second being valid.
2-84
MITEL [ MITEL NETWORKS CORPORATION ]
