MT8986
Stream Pair Selection Register - Read/Write (ONLY PROVIDED IN THE 44 PIN PACKAGES)
7
6
5
4
3
2
1
0
X
X
SPA2 SPA1
SPA0 SPB2 SPB1 SPB0
BIT
5-3
NAME
DESCRIPTION
SPA2-0
Stream Pair A selection. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPA2
SPA1
SPA0
Stream Pair A Connected
STi2 / STo2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
STi3 / STo3
STi4 / STo4
STi5 / STo5
STi6 / STo6
STi7 / STo7
STi8 / STo8
STi9 / STo9
2-0
SPB2-0
Stream Pair B selection. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPB2
SPB1
SPB0
Stream Pair B Connected
STi2 / STo2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
STi3 / STo3
STi4 / STo4
STi5 / STo5
STi6 / STo6
STi7 / STo7
STi8 / STo8
STi9 / STo9
These bits are only used when the Switching Configuration bits enable stream pair selection capability (SCB 1-0 =10) and the Input Data Rate
Selection bits enable 2 Mb/s operation (IDR-0 = 00). In all other modes, the contents of this register are ignored.
Figure 7 - Stream Pair Selection (SPS) Register
x=Don’t care
Frame Input Offset Register - Read/Write
7
6
5
4
3
2
1
0
OFB2 OFB1 OFB0
X
X
X
X
X
BIT
7-5
NAME
DESCRIPTION
OFB2-0
Offset Bits 2-0. These three bits define the time it takes the Serial Interface receiver to
recognize and store the first bit of the serial input streams; i.e., to start assuming a new
internal frame. The input frame offset can be selected to be up to 4 CK clock periods from
the time when frame pulse input signal is applied to the FR input.
OFB2
OFB1
OFB0
Number of Clock Periods
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal Operation. No bit offsetting.
1
2
3
4
Reserved
Reserved
Reserved
If frame input offset operation is not required, this register should be cleared by the CPU during system initialization.
Figure 8 - Frame Input Offset (FIO) Register
x=Don’t care
2-81