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MT8985AL 参数 Datasheet PDF下载

MT8985AL图片预览
型号: MT8985AL
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS⑩系列增强型数字式开关 [CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch]
分类和应用: 开关
文件页数/大小: 18 页 / 326 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8985
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
40 PIN PLASTIC DIP
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
44 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
40
DIP
44
44
PLCC QFP
Name
Description
1
2-9
10
11
2
40
DTA
Data Acknowledgement
(Open Drain Output). This active low output indicates that
a data bus transfer is complete. A pull-up resistor is required at this output.
3-5 41-43 STi0-
ST-BUS Input 0 to 7 (Inputs).
Serial data input streams. These streams have 32
7-11 1-5
STi7 channels at data rates of 2.048 Mbit/s.
12
13
6
7
V
DD
F0i
+5 Volt Power Supply rail.
Frame Pulse (Input):
This input accepts and automatically identifies frame
synchronization signals formatted according to different backplane specifications
such as ST-BUS and GCI.
Clock (Input).
4.096 MHz serial clock for shifting data in and out of the data streams.
12
14
8
C4i
13-18 15-17 9-11 A0-A5
Address 0 to 5 (Inputs).
These lines provide the address to MT8985 internal
19-21 13-15
registers.
19
22
16
DS
Data Strobe (Input).
This is the input for the active high data strobe on the
microprocessor interface. This input operates with CS to enable the internal read and
write generation.
Read/Write (Input).
This input controls the direction of the data bus lines (D0-D7)
during a microprocessor access.
20
23
17
R/W
2-46
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
44 PIN QFP
12
13
14
15
16
17
18
19
20
21
22
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
1819 20 21 22 23 24 25 26 27 28