MT8985
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the matrices, and put all other
channels into the high impedance state. Care should
be taken that no two connected ST-BUS outputs
drive the bus simultaneously. When this process is
complete, the microprocessor controlling the
matrices can bring the ODE signal high to relinquish
high impedance state control to the CMH
b
0s.
time slots to carry voice, data and video (channels of
128, 256 Kb/s, ISDN H0 and others), the central
routing matrix has to guarantee constant throughput
delay to maintain the sequence integrity between
input and output channels.
Figure 7 shows an
example where the MT8985 device guarantees data
integrity when data flows from the T1/E1 to the S/U
interface links and vice-versa. Modern technologies
available today such as Frame Relay network using
dedicated fractional T1 are one of the key
applications for the MT8985 device.
Low Latency Isochronous Network
In today's local working group environment, there is
an
increasing
demand
for
solutions
on
interconnection of desktop and telephone systems
so that mixed voice, data and video services can be
grouped together in a reliable network allowing the
deployment of multimedia services. Existing
multimedia applications require a network with
Applications
Typical Exchange, PBX or Multiplexer
Figure 7 shows a typical implementation of line cards
being interconnected through a central routing matrix
that can scale up in channel capacity to
accommodate different number of ports depending
on the application. In a configuration where the
switched services utilize concatenated or grouped
To other lines
Basic Rate Line Card
Layers
2&3
Entity
ST-BUS
ST-BUS
To other lines
MT8930/31
S/U
MT8910
MT8972
C
P
U
ROUTING
MATRIX
MT8985’s
ST-BUS
T1/E1
Link
MT8940/
MT8941
MH89760/
MH89790
MT8920
µC
Primary Rate Card
Figure 7 - Typical Exchange, PBX or Multiplexer Configuration
2-52
MITEL [ MITEL NETWORKS CORPORATION ]
