MT8941B
CMOS
MT8980/81
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
V
DD
MH89790B
C4b
C2i
C2o
F0i
E8Ko
F0b
DSTi
DSTo
CSTi0
CSTi1
CSTo
OUTA
OUTB
Y
o
V
SS
RST
RxT
RxR
Mode of Operation for the MT8941B
C
R
V
DD
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
RECEIVE
TRANSMIT
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
ST-BUS
SWITCH
Crystal Clock
(16.384 MHz)
Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link
Figures 11 and 12 show how the MT8941B can be
used to synchronize the ST-BUS to the CEPT
transmission link at the master and slave ends.
Generation of ST-BUS Timing Signals
The MT8941B can source the properly formatted ST-
BUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.
Figure 13 shows two such applications using DPLL
#2. In one case, the MT8941B is in FREE-RUN
mode with an oscillator input of 16.384 MHz. In the
other case, it is in NORMAL mode with the C8Kb
input tied to V
DD
. For these applications, DPLL #2
does not make any corrections and therefore, the
output signals are free from jitter. DPLL #1 is
completely free.
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
Ai
Bi
V
SS
RST
V
DD
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN MODE
(MS0=1; MS1=0;MS2=1;
MS3=1)
MS0
MS1
MS2
MS3
F0i
C12i
MT8941B
V
DD
C4o
C4b
ST-BUS
C4o
C4b
ST-BUS
Crystal Clock
(16.384 MHz)
C2o
C2o
F0b
TIMING
SIGNALS
Crystal Clock
(16.384 MHz)
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
Ai
Bi
V
SS
RST
C2o
C2o
F0b
TIMING
SIGNALS
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
MS2=1; MS3=1)
R
V
DD
C
C
R
V
DD
Figure 13 - Generation of the ST-BUS Timing Signals
12
MITEL [ MITEL NETWORKS CORPORATION ]
