CMOS
MT8941B
MT8980/81
Crystal Clock
(12.352 MHz)
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
C16i
EN
C4o
EN
C2o
V
DD
MH89760B
C1.5i
C2i
C4b
C2o
F0i
E8Ko
ST-BUS
SWITCH
CVb
DSTi
DSTo
CSTi
CSTo
TxT
TRANSMIT
F0b
TxR
RxT
RxR
RECEIVE
T1
LINK
(1.544 Mbps)
Crystal Clock
(16.384 MHz)
V
SS
RST
Mode of Operation for the MT8941B
C
R
V
DD
DPLL #1 - NORMAL ( MS1=0)
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 10 - Synchronization at the Slave End of the T1 Transmission Link
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
EN
CV
C8Kb
Crystal Clock
(16.384 MHz)
MT8980/81
MH89790B
ST-BUS
SWITCH
DSTi
C2i
C2o
F0i
DSTo
CSTi0
CSTi1
F0b
CSTo
OUTA
TRANSMIT
OUTB
Y
o
RxT
RECEIVE
RxR
Mode of Operation for the MT8941B
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN
(MS0=1; MS1=0; MS2=1; MS3=1)
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
V
DD
C4b
C16i
EN
C4o
EN
C2o
V
SS
RST
V
DD
C
R
Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link
At the slave end of the link (Figure 10) both the
DPLLs are in NORMAL mode, with DPLL #2
providing the ST-BUS timing signals locked to the 8
kHz frame pulse (E8Ko) extracted from the received
signal on the T1 line. The regenerated frame pulse
is looped back to DPLL #1 to provide the T1 line
clock, which is the same as the master end.
The 12.352 MHz and 16.384 MHz crystal clock
sources are necessary for DPLL #1 and #2,
respectively.
Synchronization and Timing Signals for the
CEPT Transmission Link
The MT8941B can be used to provide the timing and
synchronization signals for the MH89790/790B,
Mitel’s CEPT (30+2) Digital Trunk Interface Hybrid.
Since the operational frequencies of the ST-BUS and
the CEPT primary multiplex digital trunk are the
same, only DPLL #2 is required.
11
MITEL [ MITEL NETWORKS CORPORATION ]
