MT8920B
CMOS
STi0
IACK, MS1
F0i
C4i
VDD
MMS
DTACK,
BUSY, DCS
4
3
2
1
28
27
26
•
28 PIN PDIP/CERDIP/SOIC
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
Name
C4i
F0i
Description
‡
4.096 MHz Clock.
The ST-BUS timing clock used to establish bit cell boundaries for the serial
bus.
Framing Pulse.
A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS
stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of
a frame.
Interrupt Acknowledge (Mode 1).
This active low input signals that the current bus cycle is
an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will
output a user-programmed vector number on D
0
- D
7
indicating the source of the interrupt.
Mode Select 1 (Mode 2,3).
This input is used to select the device operating modes. A low
applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)
ST-BUS Input 0.
This is the input for the 2048 kbit/s ST-BUS serial data stream.
Chip Select.
This active low input is used to select the STPA for a parallel access .
Data Strobe (Mode 1).
This active low input indicates to the STPA that valid data is on the data
bus during a write operation or that the STPA must output valid data on the data bus during a
read operation.
Output Enable (Mode 2).
This active low input enables the data bus driver outputs.
Output Enable (Mode 3).
This active low output indicates that the selected device is to be
read and that the data bus is available for data transfer.
Read/Write (Mode 1,2).
This input defines the data bus transfer as a read (R/W = 1) or a write
(R/W= 0) cycle.
Write Enable (Mode 3).
This active low output indicates the data on the data bus is to be
written into the selected location of an external device.
3
IACK
MS1
4
5
6
STi0
CS
DS
OE
OE
7
R/W
WE
8-12
A0-A4
Address Bus (Mode 1,2).
These inputs are used to select the internal registers and two-port
memories of the STPA.
A0-A4
Address Bus (Mode 3).
These address outputs are generated by the STPA and reflect the
position in internal RAM where the information will be fetched from or stored in. Addresses
generated in this mode are used to access external devices for direct memory transfer.
3-4
A4
A5, STCH
VSS
D0
D1
D2
D3
C4i
F0i
IACK, MS1
STi0
CS
DS, OE
R/W, WE
A0
A1
A2
A3
A4
A5, STCH
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
MMS
DTACK, BUSY, DCS
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0
12
13
14
15
16
17
18
CS
DS, OE
R/W, WE
A0
A1
A2
A3
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
28 PIN J-LEAD
MITEL [ MITEL NETWORKS CORPORATION ]
