CMOS
MT8920B
ADDRESS BITS
A
6
0
•
•
•
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
•
•
•
1
NOTES:
REGISTERS
A
1
0
•
•
•
1
0
0
1
0
0
1
1
0
0
1
1
0
0
0
•
•
•
1
A
0
0
•
•
•
1
0
1
0
0
1
0
1
0
1
0
1
0
1
A
5
0
•
•
•
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
•
•
•
0
A
4
0
•
•
•
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
1
A
3
0
•
•
•
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
•
•
•
1
A
2
0
•
•
•
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
•
•
•
1
READ
Rx0 - Channel 0
•
•
•
Rx0 - Channel 31
Control Register 1
Control Register 2
Interrupt Vector Register
Interrupt Flag Register 1
Interrupt Flag Register 2
Image Register 1
Image Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Match Byte Register 1
Match Byte Register 2
Interrupt Channel Address 1
Interrupt Channel Address 2
WRITE
Tx0 - Channel 0
•
•
•
Tx0 - Channel 31
Control Register 1
Control Register 2
Interrupt Vector Register
-
-
-
-
Interrupt Mask Register 1
Interrupt Mask Register 2
Match Byte Register 1
Match Byte Register 2
Interrupt Channel Address 1
Interrupt Channel Address 2
Tx1 - Channel 0
•
•
•
Tx1 - Channel 31
0
Rx0 - Channel 0
•
•
•
•
•
•
1
Rx0 - Channel 31
Table 2. Mode 1 Address Map
X is don’t care
A
6
is bit D
4
of Control Register 1
Bit
7
6
Name
(Unused)
IRQRST
Description
Interrupt Reset.
This bit, when set high, automatically clears the Interrupt Flag Register
and the Interrupt Image Register without these registers being serviced. This bit
automatically resets to zero after the register clear is completed.
RAM Configuration.
This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte
operation. D
5
= 0 for 32 channel; D
5
= 1 for 24 channel.
Address Bit A6.
This bit extends the addressing range for access to Tx1 memory.
Interrupt Source 2 Mode Select.
This bit configures the source 2 interrupt generator.
D
3
= 0 selects “static” interrupt mode; D
3
= 1 selects “dynamic” interrupt mode.
Interrupt Source 1 Mode Select.
This bit configures the source 1 interrupt generator.
D
2
= 0 selects “static” interrupt mode; D
2
= 1 selects “dynamic” interrupt mode.
Interrupt Source 2 Enable.
IRQ2EN = 1 enables interrupts to occur from source 2.
Interrupt Source 1 Enable.
IRQ1EN = 1 enables interrupts to occur from source 1.
Table 3. Control Register 1 Bit Definitions
3-9
5
4
3
2
1
0
RAMCON
A
6
IRQ2MODE
IRQ1MODE
IRQ2EN
IRQ1EN
MITEL [ MITEL NETWORKS CORPORATION ]
