MT8910-1
Preliminary Information
TSTin
AVSS
NC
Lout+
NC
Lout-
Lin+
Lin-
VRef
VBias
NC
28 PIN CERDIP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
DIP PLCC
1
2
3
4
1
3
5
6
L
out-
L
out+
AV
SS
TSTin
Line Out Minus.
One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q
signal, biased at V
Bias
.
Line Out Plus.
One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal,
biased at V
Bias
.
Analog Ground.
Tie to V
SS
.
I/O Structure Test Input.
When TSTen is high, TSTin is used as a source to all output
drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to V
SS
for normal operation.
Description
5
6
7
8
8
12
13
14
CDSTi
Control/Data ST-BUS Input.
A 2048 kbit/s serial PCM/data input for the D- and
C-channels in Dual mode. Unused in Single mode and should be connected to V
SS
.
DSTi
V
SS
DSTo
Data ST-BUS Input.
A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are input.
Ground.
Data ST-BUS Output.
A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are output. This output is
placed in high impedance during the unused channel times.
9
15
CDSTo
Control/Data ST-BUS Output.
A 2048 kbit/s serial PCM/data output for the D- and
C- channels in Dual mode. It is placed in high impedance in Single mode, and during the
unused channel times in Dual mode.
F0od
Delayed Frame Pulse Output.
A 244 ns wide negative going pulse indicating the end of
the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS
devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
10
16
11
18
TSTout
I/O Structure Test Output.
When TSTen is high, the TSTout provides the output of an
XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in
functional description for more details. Leave unconnected for normal operation.
MS0
MS1
Mode Select 0.
CMOS input. Refer to Table 1.
Mode Select 1.
CMOS input. Refer to Table 1.
12
13
9-4
19
20
TSTout
MS0
MS1
NT/LT
TSTen
SFb
NC
C4b
NC
F0b
NC
44 PIN PLCC
Lout-
Lout+
AVSS
TSTin
CDSTi
DSTi
VSS
DSTo
CDSTo
F0od
TSTout
MS0
MS1
NT/LT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Lin+
Lin-
VRef
VBias
AVDD
IC
VDD
MRST
OSC1
OSC2
F0b
C4b
SFb
TSTen
NC
CDSTi
NC
NC
NC
DSTi
VSS
DSTo
CDSTo
F0od
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
AVDD
NC
NC
NC
IC
VDD
MRST
OSC1
OSC2
NC
MITEL [ MITEL NETWORKS CORPORATION ]
