MT8910-1
Preliminary Information
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
40
44 43 42 41
6 5 4 3 2
Lout-
Lout+
AVSS
TSTin
CDSTi
DSTi
Lin+
Lin-
1
7
39
NC
CDSTi
NC
NC
8
38
37
36
35
34
33
32
31
30
29
AVDD
3
4
5
6
7
VRef
VBias
AVDD
IC
VDD
MRST
OSC1
OSC2
F0b
9
NC
10
11
12
13
14
15
16
NC
NC
NC
NC
DSTi
VSS
DSTo
CDSTo
F0od
NC
IC
VSS
VDD
DSTo
CDSTo
F0od
TSTout
MS0
8
9
MRST
OSC1
OSC2
NC
10
11
12
13
14
17
18 19 20 21 22 23 24 25 26 27 28
C4b
SFb
TSTen
MS1
NT/LT
28 PIN CERDIP
44 PIN PLCC
Figure 2 - Pin Connections
Description
Pin Description
Pin #
Name
DIP PLCC
1
1
L
Line Out Minus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q
signal, biased at V
out-
.
Bias
2
3
L
Line Out Plus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal,
biased at V
out+
.
Bias
3
4
5
6
AV
Analog Ground. Tie to V
.
SS
SS
TSTin I/O Structure Test Input. When TSTen is high, TSTin is used as a source to all output
drivers. Refer to “I/O Structure Test" in functional description for more details. Tie to V
for normal operation.
SS
5
6
8
CDSTi Control/Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D- and
C-channels in Dual mode. Unused in Single mode and should be connected to V
.
SS
12
DSTi Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are input.
7
8
13
14
V
Ground.
SS
DSTo Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2-
channels in Single mode. In Dual mode, only the B-channels are output. This output is
placed in high impedance during the unused channel times.
9
15
16
18
CDSTo Control/Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D- and
C- channels in Dual mode. It is placed in high impedance in Single mode, and during the
unused channel times in Dual mode.
10
11
F0od Delayed Frame Pulse Output. A 244 ns wide negative going pulse indicating the end of
the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS
devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
TSTout I/O Structure Test Output. When TSTen is high, the TSTout provides the output of an
XOR chain which is sourced from all digital inputs. Refer to “I/O Structure Test" in
functional description for more details. Leave unconnected for normal operation.
12
13
19
20
MS0 Mode Select 0. CMOS input. Refer to Table 1.
MS1 Mode Select 1. CMOS input. Refer to Table 1.
9-4
MITEL [ MITEL NETWORKS CORPORATION ]
