®
CMOS ST-BUS™ FAMILY
MT8910-1
Digital Subscriber Line Interface Circuit
Preliminary Information
Features
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Compatible with ISDN U-Interface standard
Over 40dB (
@
40 kHz) of loop attenuation
Full duplex transmission over single twisted
pair
Advanced echo cancelling technology
High performance 2B1Q line code
Full activation/deactivation state machine
QSNR and line attenuation diagnostics
Frame and superframe synchronization
On-chip 15 second timer
Insertion loss measurement test signal & quiet
mode
Mitel ST-BUS compatible
Single 5V power supply
ISSUE 1
August 1993
Ordering Information
MT8910-1AC 28 Pin Ceramic DIP
MT8910-1AP
44 Pin PLCC
0°C to +70°C
Description
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC) is designed to provide ISDN basic
rate access (2B+D) at the U-interface. Full duplex
digital transmission at 160 kbit/s on a single twisted
pair is achieved using echo cancelling hybrid (ECH)
technology.
This, in conjunction with the high
performance 2B1Q line code, allows the DSLIC to
meet the loop length requirements of the digital
subscriber loops at the U-interface over the entire
non-loaded telephone loop plant.
The MT8910-1 is compatible with the complete
range of Mitel Semiconductor ISDN components
through the use of the ST-BUS interface.
Applications
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ISDN NT1 and NT2 DSL interface
Digital PABX line cards and telephone sets
Digital multiplexers and concentrators
Pair gain system
DSTi
CDSTi
Transmit
Interface
Scrambler
& Encoder
DAC and
Tx Filter
+
Lout+
MRST
F0b
C4b
SFb
F0od
MS0
MS1
NT/LT
Control
Register
Jitter
Compen-
sator
Linear
Echo
Canceller
Non-
Linear
Compen-
sator
-
Lout-
Tone
Detector
TRANSMIT/
RECEIVE TIMING
& CONTROL
INTERFACE
Framing
&
Maintenance
Decision
Feedback
Equalizer
2nd Order
PDM ADC
Status
Register
Quantizer
FIR
Digital Filter
CDSTo
DSTo
Receive
Interface
Descrambler,
Decoder &
Diagnostics
Timing
Adaptation
Circuit
Bias &
Voltage Ref.
Lin+
Lin-
VSS
AVSS
VDD
AVDD
OSC2
OSC1
TSTin
TSTout TSTen VRef
VBias
Figure 1 - Functional Block Diagram
9-3