Preliminary Information
The reset state consists of two substates, the
receive reset state and full reset state. The full reset
state is entered following a power-up or after the
expiry of the receive reset timer (40 ms). The
receive reset state is a transient state which is
entered once the DSLIC has detected a loss of
received signal while the transceiver is not
transmitting. In this state, the transceiver will not
initiate the start-up sequence but is capable of
responding to the appropriate activation tone. When
the timer in the receive reset state has timed out (40
ms), the transceiver enters the full reset state.
All timers surrounding the reset states are included
in the DSLIC and have been set as per the ANSI-
T1.601-1988:
•
•
Failure to complete a start-up sequence
timer is set at 15 seconds.
Loss of received signal timer is set at
480 ms as is the loss of
synchronization.
The receive reset state timer is set to
40 ms.
A fourth timer (not specified in ANSI
T1.601-1988) has been included which
will restrict the time to 520 ms for a
deactivation sequence.
MT8910-1
The MT8910-1 is production tested for error free
performance for 2.5 sec (20,000 ST-BUS) frames
over a 4.6km (15 kft) 26 AWG simulated loop
(equivalent to 40dB attenuation @ 40 kHz).
ST-BUS Interface
The ST-BUS is a synchronous time division
multiplexed serial bussing scheme with data streams
operating at 2048 kbit/s configured as 32, 64 kbit/s
channels (refer to Figure 7). Synchronization of the
data transfer is provided from a frame pulse which
identifies the frame boundaries and repeats at an 8
KHz rate. Figure 7 shows how the frame pulse (F0b)
defines the ST-BUS frame boundaries. All data is
clocked into the device on the rising edge of the
4096 kHz clock (C4b) three quarters of the way into
the bit cell, while data is clocked out on the falling
edge of the 4096 kHz clock at the start of the bit cell.
The bits on the ST-BUS are numbered bit 7 to bit 0
as outlined in Figure 7. Information transferred from
the system port to the line port, will maintain the
integrity of the bit order.
All timing signals, i.e., F0b, C4b and SFb, are
bidirectional. The I/O configuration of these pins is
controlled by the mode of operation (LT or NT). In
the LT mode, these timing signals must be supplied
from an external source and the MT8910-1 will in
turn uses these timing signals to transfer information
to and from the line port or the ST-BUS port. In the
NT mode, timing is generated from an on board
digital phase locked loop which extracts timing from
the received data on the DSL and generates the
system frame pulse (F0b), the system 4096 kHz
clock (C4b) and the system superframe pulse (SFb).
The superframe timing signal (SFb) is an active low
signal with a period of 12ms which is required to
provide a reference for structuring the maintenance
channel (M channel). In the LT mode, the SFb is an
input which, when set low during the system frame
pulse (F0b), will set the phase of the transmit
superframe. As an alternative, the SFb pin can be
tied high and the device will automatically establish
•
•
The DSLIC will enter a deactivated state on the
assertion of a deactivation request (setting the Start/
Stop bit to 0 in Control Register 1,
and the
subsequent loss of the received signal). Once the
deactivation process has been completed, the
request for activation can follow a warm start
process as defined in ANSI T1.601-1988.
Loop Performance
The MT8910-1 operates on a digital subscriber line
(DSL) which is a two wire twisted pair metallic
medium typically used for transmission between the
central office (LT) and the customer premise
equipment (more commonly referred to as "Basic
Access Interface on the Network side of the NT").
F0b
C4b
ST-BUS
Bit CHANNEL 31
BIT 0
Cells
CHANNEL 0
BIT 7
CHANNEL 0
BIT 6
CHANNEL 0
BIT 5
CHANNEL 0
BIT 4
CHANNEL 0
BIT 3
CHANNEL 0
BIT 2
Figure 7 - ST-BUS Functional Timing
9-11
MITEL [ MITEL NETWORKS CORPORATION ]
