Preliminary Information
Pin Description (continued)
Pin #
Name
DIP PLCC
14
15
21
22
NT/LT
TSTen
Description
MT8910-1
NT/LT Mode Select.
CMOS Input. When high, the DSLIC is setup in NT mode. When
low, LT mode is selected.
I/O Structure Test Enable Input.
This active high input enables the built-in test of all
digital input and output structures. Refer to “I/O Structure Test" in functional description for
more details. Tie to V
SS
for normal operation.
Superframe Pulse.
In LT mode, an input pulse once every superframe (12 ms) which,
when low during a falling edge of C4b within an F0b low pulse, sets the transmit
superframe boundary.
In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the
transmit superframe. In NT mode, the superframe timing is generated from the line signal
time base and, as such, SFb will only be valid once the transceiver has achieved full
activation.
16
23
SFb
17
18
25
27
C4b
F0b
4096 kHz Data Clock.
In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096
kHz ST-BUS clock output frequency locked to the line signal.
Frame Pulse.
In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS
channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating
the start of the active ST-BUS channel times.
Oscillator Output.
When the MT8910-1 operates with an External Clock (typically LT
mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm
clock (see “10.24 MHz Clock Interface" section).
When operating with a crystal (typically NT mode) connect one lead of the fundamental
mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
19
30
OSC2
20
31
OSC1
Oscillator Input.
When the DSLIC operates with an External Clock (typically LT mode)
connect OSC1 to the input of an external inverter (see Fig.11).
When operating with a crystal (typically NT mode) connect the other lead of the
fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
21
22
23
24
25
26
27
28
32
33
34
38
41
42
43
44
2,4,7,
9 -11,
17,24
26,28
29,35
36,37
39,40
MRST
V
DD
IC
AV
DD
V
Bias
V
Ref
L
in-
L
in+
NC
Master Reset.
Active low CMOS input performs a master reset of the DSLIC.
Power Supply Input.
Internal Connection.
Leave unconnected.
Analog Power Supply.
Connect to V
DD
.
Bias Voltage.
Decouple to AV
SS
through a 1.0 µF ceramic capacitor.
Reference Voltage.
Decouple to AV
SS
through a 1.0 µF ceramic capacitor.
Line Signal Input Minus.
Internally biased at V
Bias.
Line Signal Input Plus.
Internally biased at V
Bias.
No Connection.
Leave circuit open.
9-5
MITEL [ MITEL NETWORKS CORPORATION ]
