MT88L89
Advance Information
tRWH
tRWS
DS
Q clk*
A0-A15
(RS0)
16 bytes of Addr
R/W(read)
tDDR
tDHR
Read Data
(D3-D0)
R/W (write)
➀
tDSW
tDHW
Write data
(D3-D0)
➀
tCSS
tCSH
tAH
tAS
tAS
CS = (E + Q).Addr [MC6809]
tAH
CS = VMA.Addr [MC6800, MC6802]
*microprocessor pin
➀
tCSS
tCSH
Figure 16 - MC6800/MC6802/MC6809 Timing Diagram
➀ tDSW is from data to DS falling edge; tCSH is from DS rising edge to CS rising edge
tRWS
DS
tRWH
R/W
tDHR
tDDR
tAS
Read
AD3-AD0
(RS0, D0-D3)
Addr
Addr
Data
Write
AD3-AD0
(RS0-D0-D3)
Data
tDHW
tDSW
tAH
tCSH
Addr *
non-mux
High Byte of Addr
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 17 - MC68HC11 Bus Timing (with multiplexed address and data buses)
4-142
MITEL [ MITEL NETWORKS CORPORATION ]
