MH89790B
BIT
7
6
5
4
3
Preliminary Information
DESCRIPTION
Frame Sync:
This bit goes to ‘1‘ to indicate a loss of frame alignment synchronization by the
MH89790B. It goes to ‘0‘ when frame synchronization is detected.
Multiframe Sync:
This bit goes to ‘1‘ to indicate a loss of multiframe synchronization by the
MH89790B. It goes to ‘0‘ when multiframe synchronization is detected.
Frame Alignment Error:
This bit changes state when 16 or more errors have been detected in
the frame alignment signal. It will not change state more than once every 128 ms.
Control Slip:
This bit changes state when a slip occurs between the received CEPT 2048 kbit/s
link and the 2048 kbit/s ST-BUS.
Receive Alarm Indication Signal:
This bit goes to ‘1‘ to signal that an all-ones alarm signal has
been detected on the received CEPT 2048 kbit/s link. It goes to ’0’ when the all-ones alarm
signal is removed.
Receive Timeslot 16 Alarm Indication Signal:
This bit goes to ‘1‘ to signal that an all-ones
alarm signal has been detected on channel 16 of the received CEPT 2048 kbit/s link. It goes to
‘0‘ when the all-ones alarm signal is removed.
External Status:
This bit contains the data sampled once per frame at the XSt pin.
(Unused).
NAME
TFSYN
MFSYN
ERR
SLIP
RXAIS
2
RXTS16AIS
1
0
XSt
N/A
Table 14. Master Status Word 1 (MSW1): Data Format for CSTo Channel 18
BIT
7-3
2-0
NAME
TxTSC
TxBTC
DESCRIPTION
Transmit Timeslot Count:
The value of these five bits indicate the timeslot count between the
ST-BUS frame pulse and the rising edge of E8Ko.
Transmit Bit Count:
The value of these three bits indicate the bit position within the timeslot
count reported in TxTSC above.
Table 15. Phase Status Word (PSW): Data Format for CSTo Channel 19
BIT
7-0
NAME
CERC
DESCRIPTION
CRC Error Counter:
This byte is the CRC error counter. The counter will wrap around once it
reaches FF count. If maintenance option is activated, the counter will reset once per second.
Table 16. CRC Error Count: Data Format for CSTo Channel 20
BIT
7
6
5-4
3
2
NAME
Si2
Si1
NA
CRCTimer
CRCRef
DESCRIPTION
The received Si bit in frame 15 is reported in this bit. Si2 will be updated after each
RXMF pulse (pin 23).
The received Si bit in frame 13 is reported in this bit. Si1 will be updated after each
RXMF pulse (pin 23).
Unused.
CRC Timer:
Transition from 1 to 0 indicates the start of one second interval in which CRC errors
are accumulated. This bit stay high for 8 ms.
CRC Reframe:
A ’1’ indicates that the receive CRC multiframe synchronization could not be
found within the time out period of 8 ms after detecting frame synchronization. This bit will go low
if CRCSync goes low or if Maintenance is not activated.
CRC Sync:
A ’0’ indicates that CRC multiframing has been detected.
Frame Count:
This is the ninth and most significant bit of the Phase Status Word (see Table 15).
If the phase status word is incrementing, this bit will toggle when the phase reading exceeds
ST-BUS channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the
reading goes below ST-BUS channel 0, bit 0.
1
0
CRCSync
FrmPhase
Table 17. Master Status Word 2 (MSW2): Data Format for CSTo Channel 21
4-198
MITEL [ MITEL NETWORKS CORPORATION ]
