MH89770
Preliminary Information
AC Electrical Characteristics† - DS1 Link Timing (Figure 28 & 29)
‡
Parameters
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Transmit FDL Setup Time
Transmit FDL Hold Time
Receive FDL Output Delay
Facility Data Link Clock Delay
tDLS
tDLH
tDLOD
tFCD
110
70
ns
ns
ns
ns
0
50pF Load
50pF Load
135
† Timing is over recommended temperature & power supply voltage ranges.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Frame 1
Frame 12/24
Frame 2
F0i
C2i
RxFDLClk
RxFDL
TxFDLClk
TxFDL
Figure 28 - Clock & Frame Alignment for RxFDL and TxFDL
V
V
IH
C2i
IL
t
FCD
V
V
TxFDLClk
or
RxFDLClk
OH
OL
t
DLOD
V
OH
RxFDL
TxFDL
V
OL
t
t
DLS
DLH
V
IH
V
IL
Figure 29 - Facility Data Link Timing
4-156
MITEL [ MITEL NETWORKS CORPORATION ]
