ML2002 Preliminary
ꢀ MLS Interface
MiniLogic Device corporation’s serial interface designed for LCD cascading structure. The First IC will
be treated as master IC and receive command from MCU. Then it processed to send out to the preceding
slave IC in the cascading structure. In 2 pin mode, the master IC will send out ACK though the DIN pin
to acknowledge the command/data sent by the MCU, if in 4 pin mode; it would be the LAI pin. Transfer
is initiated by START and ends by STOP. If there is any error in the transfer, like couldn’t receive ACK
from LCD driver, then MCU could send START and STOP repeatedly, to restart the communication or by
disabling the IC by connect BCEI to VDD and then enable it again.
The interface is initiated by a START and ends with a STOP.
ꢀ Clock architecture
The built-in clock has a control status register on address (00H) to control the alarm and start/stop of the
clock. Then memory address from 01H to 07H are as counters storing the seconds up to years value.
Alarm registers address from 08H to 0BH are defining the condition of the alarm.
ꢂ Clock Status register Address (00H)
Bit
7 to 3
2
Symbol
Value
Description
0
AF
Default value is 0
Alarm flag inactive
Alarm flag active
0 (read)
1 (read)
0 (write) Alarm flag clear
1 (write) Alarm flag unchanged
1
0
AIE
0
1
0
1
Alarm interrupt disabled
Alarm interrupt enable
Real Time Clock runs
Real Time Clock stops
STOP
P20/29
Preliminary, April 2007
MINILOGIC [ MINILOGIC DEVICE CORPORATION LIMITED ]
