ML2002 Preliminary
ꢀ Pin Description
SYMBOL
PAD
I
DESCRIPTION
External reset input (active LOW)
BRES
LGND
INT
-
I
Logic Ground
Alarm interrupt output
Logic Supply voltage
“1” – Master, “0” – Slave
LVDD
MS
DIN
-
I
I/O
Data line input, for 2 pin interface, it need to connect to a pull high resistor and
would output ACK.
Data clock input
DCLK
LAI
I
I/O
If used as Master, it would output ACK and can be connected to DIN when used as 2
pin interface. If used as slave, it is an input pin which LOAD the display onto the
LCD screen during rising edge.
LAO
O
I
Send out LOAD signal to the cascade slave ML2002 for displaying data onto LCD
screen.
Enable Chip for receive data/command in the DIN pin
CEI
O
O
I
Send out chip enable signal to the following cascade slave IC
Data output from the display data RAM
Input clock, count number of rising edge clock
Output High on the 16th clock from CNT
32768Hz Oscillator input
CEO
DOUT
CNT
Q15
O
I
FIN
4,2,1Hz
250/125 Hz
125/62 Hz
LCLK
O
O
O
I
4, 2, 1Hz clock output
125Hz clock output for static/ 250 clock output for 1/2 duty
62Hz clock output for static/125 clock output for 1/2 duty
LCD Clock signal frequency
SEG1 .. SEG48
COM1A / B
PVDD
O
O
-
Segment output
Common output
Power VDD supply
1/2 PVDD LCD driving voltage
“1” – Halfduty, “0” – Static
1/2 PVDD
1/2 Duty
I
I
I
Common Enable. “0” – Enable, “1” – Disable
Test mode. “0” – Normal mode, “1” – Testing Mode
32K internal clock output
,
CEN1A CEN1B
T0
OOUT
I
O
I
Crystal oscillator enable. “0” – Enable, “1” – Disable
COEN
IOEN
I
I
I
32K internal clock enable. “0” – Enable, “1” – Disable
1/2 PVDD enable. “0” – Enable, “1” – Disable
HPVDDEN
Blink control circuit enable “0” – Enable, “1” – Disable
BEN
BCLK
OSC+ / -
SYNC
TFI
I
I
Blink clock input
Crystal oscillator input
I/O
I
To synchronize COMMON signal to the following cascade IC
2/4 pin interface, “1” - 2pin , “0” - 4pin
SYEN
I
SYNC enable. If in Master mode, SYNC will output signal to the next cascade IC,
but in slave mode, SYEN is “1” – SYNC output, “0” – SYNC will be high
impredence.
TOUT
DUM1,2,3
O
-
When select 4pin interface, it would output timer data.
Dummy Pad, Left it open only
Note : 1. In cascade format of ML2002(ie. ML2002-2U and –3U), one pin is the input of current ML2002
and the other is for the connection with the corresponding input pin of next ML2002.
2. Condition : FIN = 32 KHz Clock.
P19/29
Preliminary, April 2007
MINILOGIC [ MINILOGIC DEVICE CORPORATION LIMITED ]
