AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
COLUMN
(A2-A8 at CAS)
ROW
(A0-A8 at RAS)
DQ1
COLUMN MASK (A0,A1)
ON THE DQ INPUTS AT CAS
DQ2
DQ3
DQ4
CAS
D1
MASK
DATA
REGISTER
D2
D3
D4
4
(DQ1)
(DQ2)
(DQ3)
(DQ4)
MUX
4
DQ1
DQ2
DQ3
DQ4
RAS * DSF
LOAD
COLOR
REGISTER
RAS
COLOR REGISTER
(must be previously loaded)
Figure 3
BLOCK WRITE EXAMPLE
BLOCK WRITE
If DSF is HIGH when
/
C
/
A
/
S goes LOW, the AS42C4256
will perform a BLOCK WRITE cycle instead of a normal
WRITE cycle. In BLOCK WRITE cycles, the contents of the
color register are directly written to four adjacent column
locations (see Figure 3). The color register must be loaded
prior to beginning BLOCK WRITE cycles (see LOAD
COLOR REGISTER). Each DQ location of the color register
is written to the four column locations (or any of the four
that are enabled) in the corresponding DQ bit plane.
The row is addressed as in a normal DRAM WRITE cycle.
AS42C4256 883C
REV. 3/97
DS000016
However, when
/
C
/
A
/
S goes LOW only the A2-A8 inputs are
used. A2-A8 specify the “block” of four adjacent column
locations that will be accessed. The DQ inputs are then used
to determine what combination of the four column loca-
tions will be changed. DQ1 acts as a write enable for column
location A0 = 0, A1 = 0; DQ2 controls column location
A0 = 1, A1 = 0; DQ3 controls A0 = 0, A1 = 1; and DQ4 controls
A0 = 1, A1 = 1. The write enable controls are active HIGH;
the WRITE function is enabled by a logic 1 and disabled by
a logic 0.
3-33
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MICROSS [ MICROSS COMPONENTS ]
