AS42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
SPLIT READ TRANSFER (SPLIT DRAM-TO-SAM
TRANSFER)
The SPLIT READ TRANSFER (SRT) cycle eliminates the
critical transfer timing required to maintain a continuous
serial output data stream. When using normal TRANSFER
cycles, the REAL-TIME READ TRANSFER cycle has to
occur immediately after the last bit of “old data” was
clocked out of the SAM port.
When using the SPLIT TRANSFER mode, the SAM is
divided into an upper half and a lower half. While data is
being serially read from one half of the SAM, new DRAM
data may be transferred to the other half. The transfer may
occur at any time while the other half is sending data and
need not be synchronized with the SC clock.
Figure 4 shows a typical SPLIT READ TRANSFER initia-
tion sequence. The normal READ TRANSFER is first per-
formed,followed by a SPLITREAD TRANSFERofthe same
row to the upper half of the SAM. The SRT to the upper half
is optional and need only be done if the Tap for the upper
half is ≠ 0. Serial access continues, and when the SAM
address counter reaches 255 (“A8” = 0, A0-A7 = 1), the new
Tap address is loaded for the next half (“A8” = 1, A0-A7 =
Tap) and the QSF output goes HIGH. Once the serial access
has switched to the upper SAM, new data may be trans-
ferred to the lower SAM. The controller must wait for the
state of QSF to change and then the new data may be
transferred to the SAM half not being accessed. For
example, the next step in Figure 4 would be to wait until
QSFwent LOW (indicating that row-1data is shifting out of
the lower SAM) and then transfer the upper half of row 1 to
the upper SAM. If the half boundary is reached before an
SRT is done for the next half a Tap address of “0” will be
used. Access will start at 0 if going to the lower half, or 256
if going to the upper half. See Figure 5.
The /T/R/ (?O/E) tim ing is also relaxed for SPLIT
TRANSFER cycles. The rising edge of TR/ (OE) is not used
to complete the TRANSFER cycle and therefore is inde-
pendent of the rising edges of RAS or CAS. The transfer
timing is generated internally for SPLIT TRANSFER cycles.
A SPLIT READ TRANSFER does not change the direction
of the SAM port.
A normal, non-split READ TRANSFER cycle must pre-
cede any sequence of SPLIT READ TRANSFER cycles to set
SAM I/ O direction and provide a reference to which half of
the SAM the access will begin. Then SPLIT READ TRANS-
FERS may be initiated by taking DSF HIGH when RAS
goes LOW during the TRANSFER cycle. As in nonsplit
transfers, the row address is used to specify the DRAM row
to be transferred. The column address, A0-A7, is used to
input theSAM Tap address.Addresspin A8isa “don’t care”
when the Tap address is loaded at the HIGH-to-LOW
transition of CAS. It is internally generated so that the
SPLIT TRANSFER will be to the SAM half not currently
being accessed.
WRITE TRANSFER (SAM-TO-DRAM TRANSFER)
The operation ofthe WRITETRANSFERisidenticalto the
READ TRANSFER described previously except (ME)/ WE
and SE must be LOW when RAS goes LOW. The row
address indicates the DRAM row to which the SAM data
registers will be written. The column address (Tap) indi-
cates the starting address of the next SERIAL INPUT cycle
for the SAM data registers. A WRITE TRANSFER changes
the direction ofthe SAM I/ O buffers to the input mode.QFS
is LOW if access is to the lower half of the SAM, and HIGH
if access is to the upper half.
LOWER HALF
NO SRT
UPPER HALF
NO SRT
0
TAP
255
256
511
Start Split
Figure 5
SPLIT SAM TRANSFER
AS42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-36
MICROSS [ MICROSS COMPONENTS ]
