AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
internally. As with all DRAMs, the VRAM must be re-
freshed to maintain data. Refresh cycles must be timed so
that all 512 combinations of
/
R
/
A
/
S addresses are executed at
least every 8ms, (regardless of sequence). Micron recom-
mends evenly spaced refresh cycles for maximum data
integrity. An internal transfer between the DRAM and the
SAM counts as a refresh cycle. The SAM portion of the
VRAM is fully static and does not require any refresh.
The operation and control of the AS42C4256 are opti-
mized for high performance graphics and communication
designs. The dual port architecture is well suited to buffer-
ing the sequential data used in raster graphics display,
serial and parallel networking and data communications.
Special features, such as SPLIT READ TRANSFER and
BLOCK WRITE allow further enhancements to system
performance.
FUNCTIONAL BLOCK DIAGRAM
4
COLUMN
MASK
COLUMN ADDRESS
LATCH/BUFFER
4
8
COLUMN DECODER
4
DRAM
OUTPUT
BUFFERS
9
DQ1
512
SENSE AMPLIFIERS
512
COLOR
REGISTER
M
A
S
K
4
WRITE
CONTROL
LOGIC
4
DQ4
4
MUX
4
4
ROW DECODER
ROW ADDRESS
LATCH/BUFFER
4
4
DRAM
INPUT
BUFFERS
4
A0-A8
9
9
512
512 x 512 x 4
DRAM ARRAY
MASK DATA
REGISTER
MASKED WRITE
CONTROL
LOGIC
BLOCK
WRITE
CONTROL
LOGIC
9
REFRESH
COUNTER
4
256
256
TIMING
GENERATOR
&
CONTROL
LOGIC
RAS
CAS
TR/OE
ME/WE
DSF
SC
SE
TRANSFER
GATE
LOWER
SAM
256
TRANSFER
GATE
UPPER
SAM
256
TRANSFER
CONTROL
SAM
OUTPUT
BUFFERS
SDQ1
SAM LOCATION
DECODER
SAM ADDRESS
LATCH/BUFFER
SAM ADDRESS
COUNTER
4
4
SAM
INPUT
BUFFERS
4
SDQ4
9
9
SPLIT SAM
STATUS & CONTROL
QSF
AS42C4256 883C
REV. 3/97
DS000016
3-28
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MICROSS [ MICROSS COMPONENTS ]
