MT42C4256 883C
256K x 4 VRAM
AUSTIN SEMICONDUCTOR, INC.
PERSISTENT MASKED WRITE
The PERSISTENT MASKED WRITE feature eliminates
the need to rewrite the mask data before each MASKED
WRITE cycle if the same mask data is being used repeat-
edly. To initiate a PERSISTENT MASKED WRITE, a LOAD
MASK REGISTER cycle is performed by taking ME/ (WE)
and DSF HIGH when RAS goes LOW. The mask data is
loaded into the internal register when CAS goes LOW.
PERSISTENT MASKED WRITE cycles may then be per-
formed by taking ME/ (WE) LOW and DSF HIGH when
RAS goes LOW. The contents of the mask data register will
then be used as the mask data for the DRAM inputs. Unlike
the NONPERSISTENT MASKED WRITE cycle, the data
present on the DQ inputs is not loaded into the mask
register when RAS falls, and the mask data register will not
be cleared at the end of the cycle. Any number of PERSIS-
TENT MASKED WRITE cycles, to any address, may be
performed without having to reload the mask data register.
Figure 2 shows the LOAD MASK REGISTER and two
PERSISTENT MASKED WRITE cycles in operation. The
LOAD MASK REGISTER and PERSISTENT MASKED
WRITE cycles allow controllers that cannot provide mask
data to the DQ pins at RAS time to perform MASKED
WRITE operations. PERSISTENT MASKED WRITE opera-
tions may be performed during FAST PAGE MODE cycles
and the same mask will apply to all addressed columns in
the addressed row.
LOAD MASK REGISTER
PERSISTENT MASKED WRITE
PERSISTENT MASKED WRITE
RAS
CAS
ME/WE
DSF
MASK
STORED
INPUT
STORED STORED
INPUT
STORED
DATA
DATA
DATA
DATA
0
1
X
0
X
1
1
0
X
1
X
1
0
APPLY
MASK
REG.
APPLY
MASK
REG.
1
0
1
0
0
1
0
0
0
1
0
0
0
1
1
(Stored in
Mask Data
Register)
BEFORE
AFTER
BEFORE
AFTER
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON’T CARE)
Figure 2
PERSISTENT MASKED WRITE EXAMPLE
MT42C4256 883C
REV. 3/97
DS000016
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
3-32
MICROSS [ MICROSS COMPONENTS ]
