AUSTIN SEMICONDUCTOR, INC.
AS42C4256 883C
256K x 4 VRAM
FUNCTIONAL DESCRIPTION
The AS42C4256 may be divided into three functional
blocks (see Figure 1): the DRAM, the transfer circuitry, and
the SAM. All of the operations described below are shown
in the AC Timing Diagrams section of this data sheet and
summarized in the Truth Table.
Note:
For dual-function pins, the function not being
discussed will be surrounded by parentheses. For
example, the
/
T
/
R/
/
O
/
E pin will be shown as
/
T
/
R/(
/
O
/
E) in
references to transfer operations.
The 18 address bits that are used to select a 4-bit word
from the 262,144 available are latched into the chip using
the A0-A8,
/
R
/
A
/
S and
/
C
/
A
/
S inputs. First, the 9 row-address
bits are set up on the address inputs and clocked into the
part when
/
R
/
A
/
S transitions from HIGH-to-LOW. Next, the
9 column address bits are set up on the address inputs and
clocked-in when
/
C
/
A
/
S goes from HIGH-to-LOW.
Note:
DRAM OPERATION
DRAM REFRESH
Like any DRAM based memory, the MT42C4256 VRAM
must be refreshed to retain data. All 512 row address
combinations must be accessed within 8ms. The MT42C4256
supports
/
C
/
A
/
S-BEFORE-/R
/
A
/
S,
/
R
/
A
/
S-ONLY and HIDDEN
types of refresh cycles.
For the
/
C
/
A
/
S-BEFORE-/R
/
A
/
S REFRESH cycle, the row ad-
dresses are generated and stored in an internal address
counter. The user need not supply any address data, and
simply must perform 512
/
C
/
A
/
S-BEFORE-/R
/
A
/
S cycles within
the 8ms time period.
The refresh address must be generated externally and
applied to A0-A8 inputs for
/
R
/
A
/
S-ONLY refresh cycles. The
DQ pins remain in a High-Z state for both the
/
R
/
A
/
S-ONLY
and
/
C
/
A
/
S-BEFORE-/R
/
A
/
S refresh cycles.
HIDDEN REFRESH cycles are performed by toggling
/
R
/
A
/
S (and keeping
/
C
/
A
/
S LOW) after a READ or WRITE
cycle. This performs
/
C
/
A
/
S-BEFORE-/R
/
A
/
S cycles but does not
disturb the DQ lines.
Any DRAM READ, WRITE, or TRANSFER cycle also
refreshes the DRAM row being accessed. The SAM portion
of the MT42C4256 is fully static and does not require any
refreshing.
DRAM READ AND WRITE CYCLES
The DRAM portion of the VRAM is nearly identical to
standard 256K x 4 DRAMs. However, because several of the
DRAM control pins are used for additional functions on
this part, several conditions that were undefined or in
“don’t care” states for the DRAM are specified for the
VRAM. These conditions are highlighted in the following
discussion. In addition, the VRAM has several special func-
tions that can be used when writing to the DRAM.
/
R
?
A
/
S also acts as a “master” chip enable for the
VRAM. If
/
R
?
A
/
S is inactive, HIGH, all other DRAM
control pins (
?
C
?
A
/
S,
/
T
/
R/
?
O
/
E,
?
M
/
E/
?
W
/
E, etc.) are “don’t
care” and may change state without effect. No DRAM
or TRANSFER cycles will be initiated without
/
R
?
A
/
S
falling.
For single port DRAMS, the
/
O
/
E pin is a “don’t care” when
/
R
/
A
/
S goes LOW. However, for the VRAM, when
/
R
/
A
/
S goes
LOW,
/
T
/
R/(/O
/
E) selects between DRAM access or TRANS-
FER cycles.
/
T
/
R/(/O
/
E) must be HIGH at the
/
R
/
A
/
S HIGH-to-
LOW transition for all DRAM operations (except
/
C
/
A
/
S-
BEFORE-/RA
/
S).
/
If (?M
/
E)/?W
/
E is HIGH when
/
C
/
A
/
S goes LOW, a DRAM
READ operation is performed and the data from the memory
cells selected will appear at the DQ1-DQ4 port. The (/T
/
R)/
/
O
/
E input must transition from HIGH-to-LOW some time
after
/
R
/
A
/
S falls to enable the DRAM output port.
For single port normal DRAMs,
?
W
/
E is a “don’t care”
when
/
R
/
A
/
S goes LOW. For the VRAM,
?
M
/
E/(?W
/
E) is used,
when
/
R
/
A
/
S goes LOW, to select between a MASKED WRITE
cycle and a normal WRITE cycle. If
?
M
/
E/(?W
/
E) is LOW at the
/
R
/
A
/
S HIGH-to-LOW transition, a MASKED WRITE opera-
tion is selected. For any DRAM access cycle (READ or
WRITE),
?
M
/
E/(?W
/
E) must be HIGH at the
/
R
/
A
/
S HIGH-to-
LOW transition. If (?M
/
E)/?W
/
E is LOW before
/
C
/
A
/
S goes
LOW, a DRAM EARLY-WRITE operation is performed and
the data present on the DQ1-DQ4 data port will be written
into the selected memory cells. If (?M
/
E)/?W
/
E goes LOW after
/
C
/
A
/
S goes LOW, a DRAM LATE-WRITE operation is per-
formed. Refer to the AC timing diagrams.
The VRAM can perform all the normal DRAM cycles
including READ, EARLY-WRITE, LATE-WRITE,
READ-MODIFY-WRITE, FAST-PAGE-MODE READ,
FAST-PAGE-MODE WRITE (Late or Early), and FAST-
PAGE-MODE READ-MODIFY-WRITE. Refer to the AC
timing parameters and diagrams in the data sheet for more
details on these operations.
AS42C4256 883C
REV. 3/97
DS000016
3-30
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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