SRAM
AS5C4009LL
Austin Semiconductor, Inc.
ACTESTCONDITIONS
50 ohms
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
167 ohms
Q
1.73V
C = 100pF
C=30pF
Fig. 1 Output Load Equivalent
NOTES
1. Overshoot: Vcc +3.0V for pulse width < 20ms.
2. Undershoot: -3V for pulse width < 20ms.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
occurring chip enable.
10. RC = Read Cycle Time.
11. Chip enable and write enable can initiate and
terminate a WRITE cycle.
12. Output enable (OE\) is inactive (HIGH).
13. Output enable (OE\) is active (LOW).
14. ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
t
6. At any given temperature and voltage condition,
t
HZCE is less than tLZCE, and tHZWE is less than
tLZWE
.
7. WE\ is HIGH for READ cycle.
15. All voltage referenced to Vss (GND).
8. Device is continuously selected. Chip enables and
output enables are held in their active state.
9. Address valid prior to, or coincident with, latest
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
V
CE\ > (VCC - 0.2V)
VIN > (VCC - 0.2V)
VCC = 2V
VCC = 3V
ICCDR
ICCDR
100
200
µA
µA
Data Retention Current
Chip Deselect to Data
Retention Time
tCDR
tR
0
5
ns
4
ms
4, 10
Operation Recovery Time
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5C4009LL
Rev. 4.0 2/01
5
MICROSS [ MICROSS COMPONENTS ]
