PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
VDR
CONDITIONS
MIN
MAX
UNITS NOTE(S)
VCC for Data Retention
2
V
Data Retention Current
Chip Deselect to DR time
Operation Recovery
10
mA
ICCDR
tCDR
V
CC = VDR = 2.0V, CS\ V
≥
CC
0
ns
ns
4
-0.3V, V
VCC - 0.3V or V
≥
IN
IN
0.3V
≤
tRC
4,11
tR
AC SWITCHING CHARACTERISTICS
READ
15ns
17ns
20ns
MTS1512K8C15L
MTS1512K8C20L
MTS1512K8C25L
PARAMETER
VCC to First Access
SYMBOL
tPOWER
tRC
MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTE(S)
100
15
-
-
-
100
20
-
-
-
100
25
-
-
-
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
READ Cycle Time
Address Access Time
15
15
-
17
17
-
20
20
-
tAC
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Ouput in High-Z
Chip Enable to Power-Up
-
-
-
tACS
tOH
3
3
0
-
3
3
0
-
3
3
0
-
-
-
-
4,7
tCLZ
7
7
-
8
8
-
8
4,6,7
tCHZ
tOE
10
-
0
-
0
-
0
-
4,7
tOLZ
tOHZ
tPU
7
-
8
-
8
4,6,7
0
-
0
-
0
-
-
Chip Disable to Power-Down
15
17
20
tPD
25ns
35ns
45ns
MTS1512K8C25L
MTS1512K8C35L
MTS1512K8C45L
PARAMETER
VCC to First Access
READ Cycle Time
SYMBOL
tPOWER
tRC
MIN
MAX
-
MIN
MAX
-
MIN
MAX
-
UNITS NOTE(S)
100
25
-
100
15
-
100
20
-
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
-
-
-
Address Access Time
Chip Enable Access Time
25
25
-
15
15
-
20
20
-
tAC
-
-
-
tACS
tOH
3
3
0
-
3
3
0
-
3
3
0
-
Output Hold from Address Change
-
-
-
4,7
tCLZ
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
10
12
-
12
15
-
15
22
-
4,6,7
tCHZ
tOE
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Ouput in High-Z
Chip Enable to Power-Up
0
-
0
-
0
-
4,7
tOLZ
tOHZ
tPU
10
-
12
-
15
-
4,6,7
0
-
0
-
0
-
Chip Disable to Power-Down
25
35
45
tPD
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
MICROSS [ MICROSS COMPONENTS ]
