PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
WRITE
15ns
17ns
20ns
MTS1512K8C15L
MTS1512K8C20L
MTS1512K8C25L
PARAMETER
SYMBOL
tWC
MIN
15
10
0
MAX
MIN
17
12
0
MAX
MIN
20
14
0
MAX
UNITS NOTE(S)
WRITE Cycle Time
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
8
-
-
-
-
-
-
-
-
-
8
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of WRITE
Address Setup Time
tCW
tAS
Address Hold from End of WRITE
Address Valid to End of WRITE
WRITE Pulse Width
0
0
0
tAH
10
10
8
12
12
9
14
14
10
0
tAW
tWP
Data Setup Time
tDS
Data Hold Time
0
0
tDH
WRITE Disable to Output in Low-Z
WRITE Enable to Output in High-Z
4
4
5
ns
ns
4,6,7
4,6,7
tWLZ
tWHZ
-
-
-
25ns
35ns
45ns
MTS1512K8C25L
MTS1512K8C35L
MTS1512K8C45L
PARAMETER
WRITE Cycle Time
SYMBOL
tWC
MIN
25
16
0
MAX
MIN
35
18
0
MAX
MIN
45
24
0
MAX
UNITS NOTE(S)
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of WRITE
Address Setup Time
tCW
tAS
Address Hold from End of WRITE
Address Valid to End of WRITE
WRITE Pulse Width
0
0
0
tAH
16
16
10
0
18
18
12
0
24
24
15
0
tAW
tWP
Data Setup Time
tDS
Data Hold Time
tDH
WRITE Disable to Output in Low-Z
WRITE Enable to Output in High-Z
5
5
5
ns
ns
4,6,7
4,6,7
tWLZ
tWHZ
10
10
12
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.