SRAM
AS8S512K32
& AS8S512K32A
Austin Semiconductor, Inc.
NOTES
1. All voltages referenced to VSS (GND).
2. -2V for pulse width <20ns.
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE
.
3. ICC is dependent on output loading and cycle rates.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
1
HZ.
unloaded, and f=
t
RC(MIN)
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in Fig. 2.
Transition is measured +/- 200 mV typical from steady state
voltage, allowing for actual tester RC time constant.
13. ICC is for 32 bit mode.
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2
V
All Inputs @ Vcc + 0.2V
or Vss + 0.2V,
VCC = 2V
CC = 3V
ICCDR
ICCDR
20
mA
mA
Data Retention Current
V
28*
CS\ = Vcc + 0.2V
Chip Deselect to Data
Retention Time
0
ns
ns
4
t
CDR
Operation Recovery Time
4, 11
t
t
RC
R
* -12 and -15 have a 32mA limit.
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR>2V
tCDR
R
t
VDR
CS\ 1-4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8S512K32 & AS8S512K32A
Rev. 6.0 6/05
8
MICROSS [ MICROSS COMPONENTS ]
