LX1691
TM
®
Enhanced Multi-Mode CCFL Controller
P
RODUCTION
D
ATA
S
HEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (
V
DDP
) ..................................................................................................... 6V
Digital Input (
ENABLE
)....................................................................... -0.3V to V
DDP
+0.5V
Analog Inputs (
I_SNS, OC_SNS, OV_SNS)
clamped to +/- 10V. Max peak current +/-100mA
Analog Inputs (
BRITE_IN
)................................................................... -0.3V to V
DDP
+0.5V
DIM_MODE
Input ................................................................................ -0.3V to V
DDP
+0.5V
DD_CLK Digital Input ........................................................................ 0.3V to V
DDP
+0.5V
Digital Output (
A
OUT
, B
OUT
) .................................................................. -0.3V to V
DDP
+0.5V
Analog Outputs (
BRITE_R, I_R, EA_OUT,BRITE_OUT
) ....................... -0.3V to V
DDP
+0.5V
Operating Temperature Range ........................................................................ -55 to 125°C
Maximum Junction Temperature ...............................................................................150°C
Package Peak Temperature for Solder Reflow (40 Seconds Maximum Exposure) ......... 255°C (+5 -0)
Note:
Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
PACKAGE PIN OUT
GND
A
OUT
B
OUT
DIM_CLK
DIM_MODE
BRITE_OUT
BRITE_R
BRITE_IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
WWW .
Microsemi
.C
OM
V
DDP
V
DDA
OP_SNS
VIN_SNS
I_SNS
EA_OUT
I_R
ENABLE
PW P
ACKAGE
(Top View)
Pb-free 100% Matte Tin Lead Finish
THERMAL DATA
PW
Plastic TSSOP 16-Pin
T
HERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
99°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JA
).
The
θ
JA
numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
P
IN
N
AME
GND
V
DDP
Ground
Voltage Input, 3.0 to 5.5V input range. V
DDP
is switched (see ENABLE) to remove power from chip. An LDO
regulator follows the switch and generates V
DDA
(see V
DDA
). The output driver stages are powered directly from
the V
DDP
input. Care must be taken in power distribution design to minimize transients and noise coupling from
V
DDP
to the V
DDA
output.
Analog V
DDA
Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on
chip V
DDA
LDO regulator. The input of the LDO is the switched V
DDP
supply. LDO output is normally 3.0V and is
used to drive all circuitry except the output buffers at AOUT and BOUT. Drop out voltage is typically 50mV (@
25°C) at 5mA, the average internal load. This output can supply up to a 5 mA external load. The output
capacitor recommended is <1000nF of the ceramic dielectric type.
A buffer N-FET driver output. 10K internal pull down, ± 100 mA peak current with 3 VDC applied to V
DDP
pin.
B buffer N-FET driver output. 10K internal pull down, ± 100 mA peak current with 3 VDC applied to V
DDP
pin.
Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for Digital
Dimming. This input can be forced to V
DDA
or VSS or any clock signal up to 1MHz. This pin is also used to
control the dimming polarity when operating in the internally clocked digital dimming mode*. If DIM_MODE is in
the open condition (Analog Dimming Mode) the DD_CLK input is tied to V
DDA
or open (internal pull-up) to select
conventional dimming polarity. It is tied to Ground for reverse polarity. Conventional polarity means that lamp
brightness increases with increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness
decreases with increasing voltage. If DIM_MODE is open and a low frequency pulse is applied to DD_CLK, lamp
current amplitude is directly proportional to the voltage at BRITE_IN, and its duty cycle follows the DD_CLK
waveform, e.g., current flows when DD_CLK is high. In this mode pulse count should be greater than fault
count..
D
ESCRIPTION
V
DDA
A
OUT
B
OUT
P
ACKAGE
D
ATA
P
ACKAGE
D
ATA
DD_CLK*
Copyright
©
2003
Rev. 1.0, 7/16/2004
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
MICROSEMI [ MICROSEMI CORPORATION ]
