VSP 94x2A
DATA SHEET
2
Table 3–8: I C bus command description, continued
Bit
Name
Description
Subaddress 8Fh (Read-only, NOT compatible to 940X family)
D3
SLS
[CP-I2C]
Line Standard At Device Output
‘0’: 100 Hz (VSP 9402A, VSP 9412A)
‘1’: 50 Hz (VSP 9432A, VSP 9442A)
D2-D0
VERSION
[CP-I2C]
Version Of VSP 94XX Family
‘001’: VSP 94x5B
‘010’: VSP 94x2A
‘011’: VSP 94x7B
‘101’: VSP 94x9C
others: reserved
Subaddress 90h (Read-only)
D7
AM50O
[CP-I2C]
Last detected Standard 50 Hz
‘0’: PAL or none
‘1’: SECAM
D6
AM60O
[CP-I2C]
Last detected Standard 60 Hz
‘0’: NTSC M or none
‘1’: NTSC44 or PAL60
D5-D0
AGCADJCV
[CP-I2C]
AGC value for ADC1
000000: smallest input range
111111: biggest input range
Subaddress 91h (Read-only)
D6-D0
VLENGTH
[CP-I2C]
Length of vertical pulse
0000000: short v
1111111: long v
Subaddress 92h (Read-only)
D7-D0
MINV
[CP-I2C]
Measured sync amplitude
00000000: smallest sync
11111111: largest sync
Subaddress 93h (Read-only)
D4-D0
PWADJCNT
[CP-I2C]
Peak White adjust counter
00000: no PW reduction
11111: largest PW reduction
Subaddress 96h (Read-only)
D0
V40STAT
[FP-I2C]
V Status bit of 40.5 MHz domain
‘0’: New write or read cycle can start
‘1’: No new write or read cycle can start
Subaddress 98h (Read-only)
D0
V36BSTAT
[BP-I2C]
V Status bit of backend 36 MHz domain
‘0’: New write or read cycle can start
‘1’: No new write or read cycle can start
94
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
