VSP 94x2A
DATA SHEET
2
Table 3–8: I C bus command description, continued
Bit
Subaddress BD
D7-D0 FRINC10-3
Name
Description
Belongs to BCh
[PP]
Subaddress BE
D2-D0 FRINC2-0
Belongs to BCh
[PP]
Subaddress C0
D7-D0 HSPPL
Hsync shift
[FP-RGB]
shift=HSPPL * 4
00000000: default
Subaddress C1
D7
FOFST
[FP-RGB]
Offset of active field at interlaced mode (line offset):
0: NALPFIPI+1 at field A, NALPFIPI at field B
1: NALPFIPI at field A, NALPFIPI+1 at field B
D2-D0
VSLPF
Vsync shift
[FP-RGB]
shift=VSLPF * 4
0000000: default
Subaddress D0
D7-D6
VBLANDEL
Refer to D1h
[BP-PM]
D5
VBLANPOL
[BP-PM]
Vertikal Blank Signal Polarity
0: positive
1: negative
D2
FSWFTL
[BP-PM]
Stability Signal of LL_HPLL
‘0’: STABLL is generated accoding to SETSTABLL
‘1’: STABLL is forced to 1 (hout synchronization enabled)
D1-D0
VBLANLEN
[BP-PM]
Refer to D2h
Subaddress D1
D7-D0 VBLANDEL[7:0]
Vertical Delay in lines from vsync to active edge of blank signal:
Blank_start=1*VBLANDEL
[BP-PM]
‘0000000000’: no delay
‘1111111111’: 1023 lines delay
Subaddress D2
D7-D0 VBLANLEN
Vertical Length in lines from start of active blank signal:
Blank_length=4*VBLANLEN
[BP-PM]
‘00000000’: no line
‘11111111’: 1020 lines
Subaddress E0
D7-D0 LBGRADDET
Threshold for gradient detected
[FP-RGB]
(int) 50: default
100
Aug. 16, 2004; 6251-552-1DS
Micronas
MICRONAS [ MICRONAS ]
